P5021 datasheet(103/155 Pages) NXP

103 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

103

waveform is not referenced to ground. See Figure 40, “Differential measurement points for rise

and fall time,” as an example for differential waveform.

Common Mode Voltage, Vcm

The common mode voltage is equal to half of the sum of the voltages between each conductor of

a balanced interchange circuit and ground. In this example, for SerDes output,

Vcm_out =(VSD_TXn +VSD_TXn) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two

complementary output voltages within a differential pair. In a system, the common mode voltage

may often differ from one component’s output to the other’s input. It may be different between the

receiver input and driver output circuits within the same component. It is also referred to as the DC

offset on some occasions.

To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a

common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak

voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because

the differential signaling environment is fully symmetrical in this example, the transmitter output’s differential swing (VOD) has

the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV.

In other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.

The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.20.2

SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding

SerDes lanes. The SerDes reference clocks inputs are SD_REF_CLK1 and SD_REF_CLK1 for SerDes bank1, SD_REF_CLK2

and SD_REF_CLK2 for SerDes bank2, SD_REF_CLK3 and SD_REF_CLK3 for SerDes bank3, and SD_REF_CLK4 and

SD_REF_CLK4 for SerDes bank4.

SerDes banks 1–4 may be used for various combinations of the following IP blocks based on the RCW Configuration field

SRDS_PRTCL:

•

SerDes bank 1: PEX1/2/3, SGMII (1.25 Gbps only) or Aurora.

•

SerDes bank 2: SGMII (1.25 or 3.125 GBaud) or XAUI.

•

SerDes bank 3: SATA, or XAUI.

•

SerDes bank 4: SATA

The following sections describe the SerDes reference clock requirements and provide application information.

2.20.2.1

SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

Figure 36. Receiver of SerDes reference clocks

Input

Amp

SD_REF_CLKn

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