P5021 datasheet(101/155 Pages) NXP

101 / 155 page

Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

101

2.19.2

GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.

This figure provides the AC test load for the GPIO.

Figure 34. GPIO AC test load

2.20

High-speed serial interfaces (HSSI)

The chip features a serializer/deserializer (SerDes) interface to be used for high-speed serial interconnect applications. The

SerDes interface can be used for PCI Express, XAUI, Aurora and SGMII data transfers.

This section describes the common portion of SerDes DC electrical specifications: the DC requirement for SerDes reference

clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.

2.20.1

Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description

and specification of differential signals.

Table 60. GPIO Input AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Unit

Notes

GPIO inputs—minimum pulse width

tPIWID

Trust inputs—minimum pulse width

tTIWID

SYSCLK

Note:

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.

2. Trust inputs are asynchronous to any visible clock. Trust inputs are required to be valid for at least tTIWID to ensure proper

operation. For low power trust input pin LP_TMP_DETECT, the voltage is VDD_LP and see Table 3.for the voltage

requirement.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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