IMX6SDLCEC datasheet(166/169 Pages) NXP

166 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

166

NXP Semiconductors

Revision History

Rev. 4

12/2014

• Table 1, "Example Orderable Part Numbers," on page 3: Speed Grade footnote added as follows:

If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.

• Table 1, "Example Orderable Part Numbers," on page 3: Added (4) devices; SCIMX6U5DVM10BC/CC

and SCIMX6S5DVM10BC/CC.

• Figure 1, “Part Number Nomenclature—i.MX 6Solo and 6DualLite”: Added Silicon Rev 1.3. to diagram

• Table 2, Modules List, UART 1–5 Description changed: baud rate up from 5MHz to 5Mbps.

• Added Figure 2, "Example Part Marking," on page 5.

• Section 1.2, “Features”: under, Miscellaneous IPs and interfaces: Changed UARTs bullet, from “up to

4.0 Mbps”, to “up to 5.0 Mbps”.

• Table 8, “Operating Ranges,” on page 29:

— Changed Run mode: VDD_ARM_IN minimum value from 1.05 to 1.125V; for operation up to 396

MHz. and changed LDO bypassed maximum value from 1.225V to 1.21V; for VDD_SOC_IN.

— Changed PCIe supply voltages; PCIE_VP/PCIE_VPTX maximum value from 1.225V to 1.21V

• Table 10, "Maximum Supply Currents," on page 29;

— Changed VDD_ARM_IN from single condition to include DualLite and Solo conditions with Maximum

current values of 2200 and 1320 mA, respectively.

— Added footnote for NVCC_LVDS2P5 supply.

• Table 38, “Reset Timing Parameters”: Removed footnote regarding SRC_POR_B rise and fall times.

• Section 4.9.3, “External Interface Module (EIM)”: Changed first paragraph to describe two systems

clocks used with EIM: ACLK_EIM_SLOW_CLK_ROOT and ACLK_EXSC (for synchronous mode).

• Table 31, “DDR I/O DDR3/DDR3L Mode AC Parameters”; Added footnote about extended range for Vix.

• Table 48, “DDR3/DDR3L Timing Parameter Table,” on page 76; Added DDR0, tCK(avg) and parameter

values. Changed symbol names DDR1 through DDR7 to include avg or base; changed minimum

parameter values for DDR4–DDR7. Added footnote about tIS and tIH base values.

• Figure 25, “DDR3 Command and Address Timing Parameters,” on page 76; Added DDR0.

• Table 49, “DDR3/DDR3L Write Cycle,” on page 77; Changed symbol names of DDR17 and DDR18 to

include base(AC150/DC100); Changed Units from tCK to tCK(avg).

• Table 46, “LPDDR2 Write Cycle,” on page 64; Changed LP21 min/max parameter values from

-0.25/+0.25 to 0.75/1.25.

• Table 42, "EIM Bus Timing Parameters," on page 55: Changed footnotes regarding the system clocks

used with EIM: from axi_clk to ACLK_EXSC or ACLK_EIM_SLOW_CLK_ROOT.

• Table 49, “DDR3/DDR3L Write Cycle,” on page 77: Changed DDR17 minimum value from 420 ps to

125 ps and DDR18 from 345 ps to 150 ps.

• Table 49, “DDR3/DDR3L Write Cycle,” on page 77: Added footnote 4.

• Table 69, "LVDS Display Bridge (LDB) Electrical Specification," on page 105: Corrected Units for Output

Voltage High and Output Voltage Low from mV to V.

• Table 71, "Electrical and Timing Information," on page 108: Moved rows tSETUP[RX] and tHOLD[RX]

to be directly under HS Line Receiver AC Specifications heading row.

• Table 96, "21 x 21 mm Supplies Contact Assignments," on page 140: Removed A1 pin.

• Table 97, "21 x 21 mm Functional Contact Assignments," on page 142: Moved rows DRAM_4,

DRAM_5, and DRAM_6 out of the i.MX 6DualLite section (shaded gray) to the i.MX 6Solo section above

DRAM_7 and (unshaded).

• Table 99, "21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6Solo," on page 156: Removed “NC” from A1 pin

location.

• Table 100, "21 x 21 mm, 0.8 mm Pitch Ball Map i.MX 6DualLite," on page 159: Removed “NC” from A1

pin location.

Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories (continued)

Rev.

Number

Date

Substantive Changes

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