IMX6SDLCEC datasheet(164/169 Pages) NXP

164 / 169 page

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

164

NXP Semiconductors

Revision History

Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories

Rev.

Number

Date

Substantive Changes

10/2016

• Figure 1, "Part Number Nomenclature—i.MX 6Solo and 6DualLite," on page 5: Added to Silicon

Revision block: Revision 1.2 and 1.3 and associated Mask ID.

• Table 6, "Absolute Maximum Ratings," on page 24:

– NVCC_DRAM maximum value changed to 1.975 V.

– Included footnote to NVCC_DRAM maximum value regarding maximum voltage allowance.

– Added row to Vin/Vout I/O supply voltage, separating DDR pins and non-DDR pins and included

footnote regarding maximum voltage allowance.

• Table 8, "Operating Ranges," on page 26: Added footnotes within the Comments column for the Run

Mode, LDO Enabled row; VDD_SOC_IN maximum values.

• Section 4.6.3, “DDR I/O DC Parameters: Added reference for more DDR details to see the MMDC

section.

Moved JEDEC standard information to footnote.

• Section 4.7.2, “DDR I/O AC Parameters: Added reference for more DDR details to see the MMDC

section.

Moved JEDEC standard information to footnote.

• Table 44, "i.MX 6Solo Supported DDR3/DDR3L/LPDDR2 Configurations," on page 63: Changed

LPDDR2 Channel column from “Dual” to “Single.”

• Table 45, "i.MX 6DualLite Supported DDR3/DDR3L/LPDDR2 Configurations," on page 64: Added

LPDDR2 Dual Channel column.

• Table 95, "21 x 21, 0.8 mm BGA Package Details," on page 139: Correction to package total thickness.

• Table 97, "21 x 21 mm Functional Contact Assignments," on page 142: DRAM_SDCKLn rows, reverted

to “Low” rather than “0” in the Value column.

IMX6SDLCEC датащи(PDF) 164 Page - NXP Semiconductors