IMX6SDLCEC datasheet(165/169 Pages) NXP

165 / 169 page

Revision History

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

165

8/2016

• Changed throughout:

- LVDDR3 to DDR3L

- Changed terminology from “floating” to “not connected”.

• Table 2, "i.MX 6Solo/6DualLite Modules List," on page 11:

- uSDHC1–4, SD/MMC and SDXC Enhanced Multi-Media Card/Secure Digital

Host Controller row:

Added new bullet at top: “Conforms to the SD Host Controller…”.

- eCSPI1-4 row: removed from the Brief Description column, “with data rate up to 52Mbit/s.”

BCH row, removed from Brief Description column, “encryption/decryption”.

• Table 3, "Special Signal Considerations," on page 21:

- GPANAIO row, modified remarks to be NXP use only.

- SRC_POR_B row: removed reference to internal POR which is not supported on device.

- TEST_MODE row: modified remarks to be NXP use only and added tie to Vss or remain unconnected.

• Table 6, "Absolute Maximum Ratings," on page 24” throughout table: clarified parameter descriptions

including adding LDO state. Clarified symbol names.

- Added row, RGMII I/O supply voltage.

- Added VDD_HIGH_CAP supply voltage row for LDO output.

- Added to USB supply voltage row: USB_OTG_CHD_B.

- All maximum voltages increased (improved).

• Section 4.1.2, “Thermal Resistance: added NOTE.

• Table 8, "Operating Ranges," on page 26: Changed minimum parameter of Run mode: LDO enabled

from 1.175 to 1.25 V.

• Section 4.2.1, “Power-Up Sequence”: Removed references to the internal POR function. Internal POR

is not supported. Removed fourth and fifth bullets.

• Section 4.2.3, “Power Supplies Usage”: Added NOTE, “When the PCIE interface is not used…”.

• Section 4.5.2, “OSC32K”: Removed battery resistor (coin cell) calculation.

• Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters”:

- Added 3 rows: Input capacitance; Startup current; and DC input current.

- Added footnote to RTC_XTALI high-level DC input voltage at the Max parameter.

- Added NOTE following table: “The Vil and Vih only apply when external clock source is used…”.

• Section 4.9.4, “Multi-Mode DDR Controller (MMDC)”: this new section added, replacing the original

section 4.9.4 “DDR SRAM Specific Parameters (DDR3/DDR3L and LPDDR2)”.

• Figure 36, "ECSPI Master Mode Timing Diagram," on page 73: Added note, “ECSPI_MOSI always…”.

• Figure 37, "ECSPI Slave Mode Timing Diagram," on page 74: Added note, “ECSPI_MOSI always

driven…”.

• Figure 42, "SDR50/SDR104 Timing," on page 81: Aligned SD4 and SD5.

• Table 54, "SDR50/SDR104 Interface Timing Specification," on page 81:

- Corrected Clock High Time ID to SD3.

- Changed SD2 and SD3 Min and max values to 0.46 and 0.54.

- Changed SD5 Max to 0.74.

• Table 64, "Camera Input Signal Cross Reference, Format, and Bits Per Cycle," on page 93: Changed

RGB565 column heading from 2 to 1 cycle.

• Table 97, "21 x 21 mm Functional Contact Assignments," on page 142:

- Table row: DRAM_SDCLK0 and DRAM_SDCLK1 changed Out of Reset Condition from Low to 0.

- Added to ZQPAD row: requirement to add resistor to GND.

6/2015

• Table 8, “Operating Ranges,” Run mode: LDO enabled row; Changed comments for VDD_ARM_IN,

from “1.05V minimum for operation up to 396MHz” to “1.125V minimum for operation up to 396MHz”.

• Table 3, “Special Signal Considerations,” XTALI/XTALO row: Changed from “The crystal must be

rated...”, to “See Hardware Development Guide”.

Table 102. i.MX 6Solo/6DualLite Data Sheet Document Past Revision Histories (continued)

Rev.

Number

Date

Substantive Changes

IMX6SDLCEC датащи(PDF) 165 Page - NXP Semiconductors

IMX6SDLCEC датащи(HTML) 165 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL