LP87702 datasheet(26/98 Pages) TI

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ms (SHUTDOWN_DELAY_SEL = 0) or 15 ms (SHUTDOWN_DELAY_SEL = 1). After the restart watchdog

returns to Long Open mode.

• The status bit (WD_SYSTEM_RESTART_FLAG) is set to indicate that a system restart has happened. The

status can be cleared by writing 1 to WD_CLR_SYSTEM_RESTART_FLAG. WD_RESET_CNTR_SEL can

be set to 10 or 11 to select restart after 2 or 4 WD expirations, respectively. The current status of the

reset counter is available in WD_RESET_CNTR_STATUS. The reset counter can be cleared by writing

WD_CLR_RESET_CNTR to 1.

Watchdog settings in WD_CTRL_1 and WD_CTRL_2 registers are locked by setting the WD_LOCK bit.

WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK = 1.

Description above is for a case where ENx pin is used for controlling power sequence and ENx pin is active.

Watchdog behavior can be slightly different depending on the OTP settings and the ENx pin state, which follows:

• When the ENx pin is used for controlling the power sequence and the ENx pin is not active, the shutdown

sequence cannot be performed. WD_RESET pulse length is fixed 31 ms.

• There is no OTP defined power sequence when the ENx pins are not used for power sequence control, and

all converters and GPOs are enabled through the I2C. WD expiration does not cause a converter disable

or enable sequence even when the OTP settings for the watchdog enable restart. In this case WD_RESET

pulse is 11 ms.

LP87702

SNVSBU3 – MARCH 2021

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LP87702 датащи(PDF) 26 Page - Texas Instruments