LP87702 datasheet(25/98 Pages) TI

25 / 98 page

An example of start-up and shutdown sequences for buck converters are shown in Figure 7-7. The start-up and

shutdown delays for Buck0 converter are 1 ms and 4 ms and for Buck1 converter 3 ms and 1 ms. The delay

settings are used only for enable or disable control with the EN signal.

ENx

Internal

BUCK0 enable

ENx

1 ms

3 ms

Internal

BUCK1 enable

1 ms

4 ms

3 ms

1 ms

4 ms

Typical sequence

Sequence with short EN low and high periods

Startup cntr

Shutdown cntr

Internal

BUCK0 enable

Internal

BUCK1 enable

Figure 7-7. Start-up and Shutdown Sequencing Example

7.3.8 Window Watchdog

Figure 7-8 shows the LP87702 watchdog's operation (for an example, when the ENx pin is used for controlling

power sequence and ENx pin is active).

WDI is the watchdog function input pin, and WD_RESET is the reset output. The WDI pin needs pulsed

within a certain timing window to avoid a watchdog expiration. The minimum pulse width is 100 µs. The

watchdog expiration always causes a reset pulse at WD_RESET output, otherwise the device behavior after

watchdog expiration is programmable. WD_RESET output polarity and mode, push-pull or open drain, are also

programmable.

Watchdog default settings are read from OTP during device start-up. Default settings in WD_CTRL_1 and

WD_CTRL_2 register can be over-written through the I2C (as long as WD_LOCK bit is not set to 1). Writing

WD_LOCK = 1 in WD_CTRL_2 register locks watchdog settings until NRST input is driven low, power cycle or

Table 7-4 shows how the long open, close, and open window periods are independently programmable. The

watchdog enters the WD Reset state when the long open or open window expires before the WDI input is

received. Also, the watchdog enters the WD Reset when the WDI is received during close window. Long open

period can be extended by a I2C write to WD_CTRL_1 or WD_CTRL_2 register; the register access initializes

the long open counter and the long open period restarts (except in Stop mode).

LP87702 behavior after WD expiration is programmable:

• When WD_RESET_CNTR_SEL = 00, system restart is disabled and converters are maintained ON.

WD_RESET pin is active for 10 ms. Watchdog returns to Long Open mode.

• When WD_RESET_CNTR_SEL = 01 (restart after first reset pulse), LP87702 performs shutdown sequence

followed by start-up sequence so the converters are disabled and re-enabled according to the OTP

programmed sequences. The device reloads OTP defaults when WD_EN_OTP_READ = 1 during start-up.

Settings valid before shutdown are maintained when the WD_EN_OTP_READ = 0. WD_RESET output pin is

active for a period of (10 ms + maximum shutdown delay). Maximum shutdown delay can be selected as 7.5

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LP87702

SNVSBU3 – MARCH 2021

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