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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 66 Page - Texas Instruments |
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LP87702 датащи(HTML) 66 Page - Texas Instruments |
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66 / 98 page  7.6.1.1.33 INT_TOP_1 Register (Offset = 20h) [reset = 0h] INT_TOP_1 is shown in Figure 7-51 and described in Table 7-43. Return to Table 7-9. Figure 7-51. INT_TOP_1 Register 7 6 5 4 3 2 1 0 I_MEAS_INT DIAG_INT BOOST_INT BUCK_INT SYNC_CLK_IN T TDIE_SD_INT TDIE_WARN_I NT OVP_INT R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 7-43. INT_TOP_1 Register Field Descriptions Bit Field Type Reset Description 7 I_MEAS_INT R 0h Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers. Write 1 to clear interrupt. 6 DIAG_INT R 0h Interrupt indicating that INT_DIAG register has a pending interrupt. The reason for the interrupt is indicated in INT_DIAG register. This bit is cleared automatically when INT_DIAG register is cleared to 0x00. 5 BOOST_INT R 0h Interrupt indicating that BOOST have a pending interrupt. The reason for the interrupt is indicated in INT_BOOST register. This bit is cleared automatically when INT_BOOST register is cleared to 0x00. 4 BUCK_INT R 0h Interrupt indicating that BUCK0 or BUCK1 have a pending interrupt. The reason for the interrupt is indicated in INT_BUCK register. This bit is cleared automatically when INT_BUCK register is cleared to 0x00. 3 SYNC_CLK_INT R 0h Latched status bit indicating that the external clock frequency became valid or invalid. Write 1 to clear interrupt. 2 TDIE_SD_INT R 0h Latched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. The converters have been disabled if they were enabled. The converters cannot be enabled if this bit is active. The actual status of the thermal warning is indicated by TDIE_SD_STAT bit in TOP_STATUS register. Write 1 to clear interrupt. Clearing TSD interrupt automatically re- enables converters. Clearing this interrupt will also clear thermal warning status. 1 TDIE_WARN_INT R 0h Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TDIE_WARN_STAT bit in TOP_STATUS register. Write 1 to clear interrupt. 0 OVP_INT R 0h Latched status bit indicating that the input voltage has exceeded the over-voltage detection level. The actual status of the over-voltage is indicated by OVP bit in TOP_STATUS register. Write 1 to clear interrupt. 7.6.1.1.34 INT_TOP_2 Register (Offset = 21h) [reset = 0h] INT_TOP_2 is shown in Figure 7-52 and described in Table 7-44. Return to Table 7-9. Figure 7-52. INT_TOP_2 Register 7 6 5 4 3 2 1 0 RESERVED RESET_REG_I NT LP87702 SNVSBU3 – MARCH 2021 www.ti.com 66 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
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