 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
LP87702 датащи(PDF) 56 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
LP87702 датащи(HTML) 56 Page - Texas Instruments |
|
|
56 / 98 page  7.6.1.1.19 PLL_CTRL Register (Offset = 12h) [reset = 2h] PLL_CTRL is shown in Figure 7-37 and described in Table 7-29. Return to Table 7-9. Figure 7-37. PLL_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EN_PLL EN_FRAC_DIV EXT_CLK_FREQ R/W-0h R/W-0h R/W-0h R/W-2h Table 7-29. PLL_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 EN_PLL R/W 0h Selection of external clock and PLL operation: 0 – Forced to internal RC oscillator. PLL disabled. 1 – PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use when available, interrupt generated if external clock appears or disappears. (Default from OTP memory) 5 EN_FRAC_DIV R/W 0h This bit must be set to '0'. 4-0 EXT_CLK_FREQ R/W 2h Frequency of the external clock (CLKIN): 0x00 – 1 MHz 0x01 – 2 MHz 0x02 – 3 MHz ... 0x16 – 23 MHz 0x17 – 24 MHz 0x18...0x1F – Reserved See electrical specification for input clock frequency tolerance. (Default from OTP memory) Note: To ensure proper operation of PLL, EXT_CLK_FREQ value must not be changed when PLL is enabled. 7.6.1.1.20 PGOOD_CTRL Register (Offset = 13h) [reset = 0h] PGOOD_CTRL is shown in Figure 7-38 and described in Table 7-30. Return to Table 7-9. Figure 7-38. PGOOD_CTRL Register 7 6 5 4 3 2 1 0 RESERVED PGOOD_WIND OW EN_PGOOD_V ANA EN_PGOOD_V MON2 EN_PGOOD_V MON1 EN_PGOOD_B OOST EN_PGOOD_B UCK1 EN_PGOOD_B UCK0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 7-30. PGOOD_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 PGOOD_WINDOW R/W 0h Voltage monitoring method for PG0 and PG1 signals: 0 - Only undervoltage monitoring. 1 - Overvoltage and undervoltage monitoring. (Default from OTP memory) Note: Changing this value during operation may cause interrupt. 5 EN_PGOOD_VANA R/W 0h Enable powergood diagnostics for VANA 0 – Disabled 1 – Enabled (Default from OTP memory) Note: Changing this value during operation may cause interrupt. LP87702 SNVSBU3 – MARCH 2021 www.ti.com 56 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
