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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 60 Page - Texas Instruments |
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LP87702 датащи(HTML) 60 Page - Texas Instruments |
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60 / 98 page  Table 7-34. PG_CTRL Register Field Descriptions (continued) Bit Field Type Reset Description 4 PG1_POL R/W 0h PG1 signal polarity. 0 – PG1 signal high when monitored outputs are valid 1 – PG1 signal low when monitored outputs are valid (Default from OTP memory) 3 PG0_MODE R/W 0h Operating mode for PG0 signal: 0 – Detecting unusual situations 1 – Showing when requested outputs are not valid. (Default from OTP memory) 2 PGOOD_FAULT_GATES_ PG0 R/W 0h Type of operation for PG0 signal: 0 – Indicates live status of monitored voltage outputs. 1 – Indicates status of PG0_FAULT register, inactive if at least one of PG0_FAULT_x bit is inactive. (Default from OTP memory) 1 PG0_OD R/W 1h PG0 signal type: 0 – Push-pull output (VANA level) 1 – Open-drain output (Default from OTP memory) 0 PG0_POL R/W 0h PG0 signal polarity. 0 – PG0 signal high when monitored outputs are valid 1 – PG0 signal low when monitored outputs are valid (Default from OTP memory) 7.6.1.1.25 PG0_CTRL Register (Offset = 18h) [reset = 0h] PG0_CTRL is shown in Figure 7-43 and described in Table 7-35. Return to Table 7-9. Figure 7-43. PG0_CTRL Register 7 6 5 4 3 2 1 0 PG0_RISE_DE LAY SEL_PG0_TWA RN SEL_PG0_VAN A SEL_PG0_VM ON2 SEL_PG0_VM ON1 SEL_PG0_BOO ST SEL_PG0_BUC K1 SEL_PG0_BUC K0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 7-35. PG0_CTRL Register Field Descriptions Bit Field Type Reset Description 7 PG0_RISE_DELAY R/W 0h 0 – PG0 rise is not delayed 1 – PG0 rise is delayed 11 ms 6 SEL_PG0_TWARN R/W 0h PG0 control from thermal warning: 0 - Masked 1 – Affecting PGOOD (Default from OTP memory) 5 SEL_PG0_VANA R/W 0h PG0 signal source control from VANA 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 4 SEL_PG0_VMON2 R/W 0h PG0 signal source control from VMON2 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 3 SEL_PG0_VMON1 R/W 0h PG0 signal source control from VMON1 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) LP87702 SNVSBU3 – MARCH 2021 www.ti.com 60 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
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