LP87702 datasheet(31/98 Pages) TI

31 / 98 page

Table 7-5. Summary of Interrupt Signals (continued)

EVENT

SAFE STATE

INTERRUPT BIT

INTERRUPT MASK

STATUS BIT

RECOVERY/INTERRUPT

CLEAR

Software requested

reset

Immediate shutdown

followed by powerup,

registers reset to default

values

RESET_REG_INT = 1

RESET_REG_MASK

N/A

Write 1 to the

RESET_REG_INT bit.

(1)

Interrupt generated during the Clock Detector operation and in case the Clock is not available when the Clock Detector is enabled.

7.3.10.3 Power-Good Information to Interrupt, PG0, and PG1 Pins

LP87702 supports both interrupt based indication of the power-good levels for various voltage settings and

uses two power-good signals, PG0 and PG1. The selection of monitored signals is independent for the interrupt

(nINT) and PG0 and PG1 signals. Each signal can include the following:

• The output voltage of one or both BUCKx converters

• The output voltage of the BOOST converter

• Input voltage of VANA

• Input voltage of VMON1 and VMON2 or both

• Thermal warning

Figure 7-9 shows the block diagram for power-good connections to PG0 and PG1 pins and interrupt.

Monitored signals are enabled in the PGOOD_CTRL register. Converter output voltage monitoring (not current

limit monitoring) can be selected for the indication. Monitoring is enabled by the EN_PGOOD_BUCKx and

EN_PGOOD_BOOST bits. The monitoring is automatically masked to prevent it from forcing PGx inactive or

causing an interrupt when a converter is disabled. Also, monitoring of VANA, VMON1, and VMON2 inputs can

be independently enabled through the PGOOD_CTRL register. The type of voltage monitoring for the PGx

signals and nINT is selected by the PGOOD_WINDOW bit. Only the undervoltage is monitored if the bit is 0

and the undervoltage and overvoltage are monitored if the bit is 1. See Section 7.3.10.1 for voltage monitoring

thresholds.

Monitoring interrupts from all the output rails, input rails, and thermal warning are combined to the nINT pin.

Dedicated mask bits are used to select which interrupts control the state of the nINT pin. See Table 7-5 for

summary of the interrupts, mask bits, and interrupt clearing.

Similarly, enabled monitoring signals from all the output rails, input rails, and thermal warning are combined to

PG0 and PG1 output pins. Register bits (SEL_PGx_x in PG0_CTRL and PG1_CTRL) select which of the signals

control the state of PG0 and PG1, respectively. The polarity and the output type (push-pull or open-drain) of PG0

and PG1 are selected by the PGx_POL and PGx_OD bits in the PG_CTRL register.

PGx is only active or asserted when all monitored input voltages and all output voltages of the monitored and

enabled converters are within the specified tolerance of the set target value.

PGx is inactive or de-asserted if any of the monitored input voltages or output voltages of the monitored and

enabled converters are outside the specified tolerance of the set target value.

When PGx_RISE_DELAY = 1, PGx is set as active or asserted with 11 ms delay from the point of time

where all the enabled power resource output voltages are within the specified tolerance for each requested or

programmed output voltage.

Thermal shutdown and VANA overvoltage protection events force the PGx to the default state (the PGx are

driven low, assuming the PGx polarity set in the OTP is active high).

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LP87702

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