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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 61 Page - Texas Instruments |
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LP87702 датащи(HTML) 61 Page - Texas Instruments |
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61 / 98 page  Table 7-35. PG0_CTRL Register Field Descriptions (continued) Bit Field Type Reset Description 2 SEL_PG0_BOOST R/W 0h PG0 signal source control from Boost 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 1 SEL_PG0_BUCK1 R/W 0h PG0 signal source control from Buck1 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 0 SEL_PG0_BUCK0 R/W 0h PG0 signal source control from Buck0 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 7.6.1.1.26 PG0_FAULT Register (Offset = 19h) [reset = 0h] PG0_FAULT is shown in Figure 7-44 and described in Table 7-36. Return to Table 7-9. Figure 7-44. PG0_FAULT Register 7 6 5 4 3 2 1 0 RESERVED PG0_FAULT_T WARN PG0_FAULT_V ANA PG0_FAULT_V MON2 PG0_FAULT_V MON1 PG0_FAULT_B OOST PG0_FAULT_B UCK1 PG0_FAULT_B UCK0 R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 7-36. PG0_FAULT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 PG0_FAULT_TWARN R 0h Source for PG0 inactive signal: 0 – TWARN has not set PG0 signal inactive. 1 – TWARN is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when TWARN is valid. 5 PG0_FAULT_VANA R 0h Source for PG0 inactive signal: 0 – VANA has not set PG0 signal inactive. 1 –VANA is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when VANA input is valid. 4 PG0_FAULT_VMON2 R 0h Source for PG0 inactive signal: 0 – VMON2 has not set PG0 signal inactive. 1 – VMON2 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when VMON2 input is valid. 3 PG0_FAULT_VMON1 R 0h Source for PG0 inactive signal: 0 – VMON1 has not set PG0 signal inactive. 1 – VMON1 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when VMON1 input is valid. 2 PG0_FAULT_BOOST R 0h Source for PG0 inactive signal: 0 – Boost has not set PG0 signal inactive. 1 – Boost is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when Boost output is valid. 1 PG0_FAULT_BUCK1 R 0h Source for PG0 inactive signal: 0 – Buck1 has not set PG0 signal inactive. 1 – Buck1 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid. www.ti.com LP87702 SNVSBU3 – MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: LP87702 |
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