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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 64 Page - Texas Instruments |
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LP87702 датащи(HTML) 64 Page - Texas Instruments |
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64 / 98 page  Table 7-39. WD_CTRL_1 Register Field Descriptions Bit Field Type Reset Description 7-6 WD_CLOSE_TIME R/W 0h Watchdog close window time select. 00 – 10 ms 01 – 20 ms 10 – 50 ms 11 – 100 ms (Default from OTP memory) 5-4 WD_OPEN_TIME R/W 0h Watchdog open window time select. 00 – 20 ms 01 – 100 ms 10 – 200 ms 11 – 600 ms (Default from OTP memory) 3-2 WD_LONG_OPEN_TIME R/W 0h Watchdog long open window time select. 00 – 200 ms 01 – 600 ms 10 – 2000 ms 11 – 5000 ms (Default from OTP memory) 1-0 WD_RESET_CNTR_SEL R/W 0h Watchdog reset counter threshold select. After the selected number of reset (WDR) pulses system restart sequence is initiated. 00 – system restart disabled 01 – 1 10 – 2 11 – 4 (Default from OTP memory) 7.6.1.1.30 WD_CTRL_2 Register (Offset = 1Dh) [reset = 1h] WD_CTRL_2 is shown in Figure 7-48 and described in Table 7-40. Return to Table 7-9. Figure 7-48. WD_CTRL_2 Register 7 6 5 4 3 2 1 0 WD_LOCK RESERVED WD_SYS_RES TART_FLAG_M ODE WD_EN_OTP_ READ WDI_PD WDR_POL WDR_OD R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h Table 7-40. WD_CTRL_2 Register Field Descriptions Bit Field Type Reset Description 7 WD_LOCK R 0h Lock bit for watchdog controls. Locks all controls to watchdog in registers WD_CTRL_1, WD_CTRL_2. Lock bit also locks itself. Once lock bit is written 1 it cannot be written 0. Only reset can clear it. 0 – Not locked 1 – Locked WD_STATUS register is not affected by WD_LOCK bit. WD_SYSTEM_RESTART_FLAG and WD_RESET_CNTR_STATUS can be cleared even if WD_LOCK=1. 6-5 RESERVED R/W 0h 4 WD_SYS_RESTART_FLA G_MODE R/W 0h WD_SYSTEM_RESTART_FLAG mode select. 0 - WD_SYSTEM_RESTART_FLAG is only a status bit. 1 – WD_SYSTEM_RESTART_FLAG prevents further system restarts until it is cleared. (Default from OTP memory) 3 WD_EN_OTP_READ R/W 0h Read OTP during system restart sequence 0 – OTP read not enabled during system restart sequence 1 – OTP read enabled during system restart sequence (Default from OTP memory) LP87702 SNVSBU3 – MARCH 2021 www.ti.com 64 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
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