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LP87702 датащи(PDF) 59 Page - Texas Instruments |
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LP87702 датащи(HTML) 59 Page - Texas Instruments |
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59 / 98 page ![]() 7.6.1.1.23 PGOOD_LEVEL_3 Register (Offset = 16h) [reset = 0h] PGOOD_LEVEL_3 is shown in Figure 7-41 and described in Table 7-33. Return to Table 7-9. Figure 7-41. PGOOD_LEVEL_3 Register 7 6 5 4 3 2 1 0 BOOST_WINDOW BOOST_THRESHOLD BUCK1_WINDOW BUCK0_WINDOW R/W-0h R/W-0h R/W-0h R/W-0h Table 7-33. PGOOD_LEVEL_3 Register Field Descriptions Bit Field Type Reset Description 7-6 BOOST_WINDOW R/W 0h Undervoltage or overvoltage threshold levels for Boost: 0x0 – ±2% 0x1 – ±4% 0x2 – ±6% 0x3 – ±8% (Default from OTP memory) 5-4 BOOST_THRESHOLD R/W 0h (Default from OTP memory) 3-2 BUCK1_WINDOW R/W 0h Overvoltage and undervoltage threshold levels for Buck1: 0x0 – ±30 mV 0x1 – ±50 mV 0x2 – ±70 mV 0x3 – ±90 mV (Default from OTP memory) 1-0 BUCK0_WINDOW R/W 0h Overvoltage and undervoltage threshold levels for Buck0: 0x0 – ±30 mV 0x1 – ±50 mV 0x2 – ±70 mV 0x3 – ±90 mV (Default from OTP memory) 7.6.1.1.24 PG_CTRL Register (Offset = 17h) [reset = 2h] PG_CTRL is shown in Figure 7-42 and described in Table 7-34. Return to Table 7-9. Figure 7-42. PG_CTRL Register 7 6 5 4 3 2 1 0 PG1_MODE PGOOD_FAUL T_GATES_PG1 RESERVED PG1_POL PG0_MODE PGOOD_FAUL T_GATES_PG0 PG0_OD PG0_POL R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h Table 7-34. PG_CTRL Register Field Descriptions Bit Field Type Reset Description 7 PG1_MODE R/W 0h Operating mode for PG1 signal: 0 – Detecting unusual situations 1 – Showing when requested outputs are not valid. (Default from OTP memory) 6 PGOOD_FAULT_GATES_ PG1 R/W 0h Type of operation for PG1 signal: 0 – Indicates live status of monitored voltage outputs. 1 – Indicates status of PG1_FAULT register, inactive if at least one of PG1_FAULT_x bit is inactive. (Default from OTP memory) 5 RESERVED R/W 0h www.ti.com LP87702 SNVSBU3 – MARCH 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: LP87702 |
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