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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 68 Page - Texas Instruments |
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LP87702 датащи(HTML) 68 Page - Texas Instruments |
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68 / 98 page  Figure 7-54. INT_BOOST Register 7 6 5 4 3 2 1 0 RESERVED BOOST_PG_IN T BOOST_SC_IN T BOOST_ILIM_I NT R/W-0h R-0h R-0h R-0h Table 7-46. INT_BOOST Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 0h 2 BOOST_PG_INT R 0h Latched status bit indicating that Boost powergood event has been detected. Write 1 to clear. 1 BOOST_SC_INT R 0h Latched status bit indicating that the Boost output voltage has fallen to input voltage level or below 2.5 V level during operation or BOOST output didn't reach 2.5 V level in 1 ms from enable. Write 1 to clear. 0 BOOST_ILIM_INT R 0h Latched status bit indicating that Boost output current limit has been triggered. Write 1 to clear. 7.6.1.1.37 INT_DIAG Register (Offset = 24h) [reset = 0h] INT_DIAG is shown in Figure 7-55 and described in Table 7-47. Return to Table 7-9. Figure 7-55. INT_DIAG Register 7 6 5 4 3 2 1 0 RESERVED VMON2_PG_IN T RESERVED VMON1_PG_IN T RESERVED VANA_PG_INT R/W-0h R-0h R/W-0h R-0h R/W-0h R-0h Table 7-47. INT_DIAG Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4 VMON2_PG_INT R 0h Latched status bit indicating that VMON2 powergood event has been detected. Write 1 to clear. 3 RESERVED R/W 0h 2 VMON1_PG_INT R 0h Latched status bit indicating that VMON1 powergood event has been detected. Write 1 to clear. 1 RESERVED R/W 0h 0 VANA_PG_INT R 0h Latched status bit indicating that VANA powergood event has been detected. Write 1 to clear. 7.6.1.1.38 TOP_STATUS Register (Offset = 25h) [reset = 0h] TOP_STATUS is shown in Figure 7-56 and described in Table 7-48. Return to Table 7-9. Figure 7-56. TOP_STATUS Register 7 6 5 4 3 2 1 0 LP87702 SNVSBU3 – MARCH 2021 www.ti.com 68 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
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