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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 62 Page - Texas Instruments |
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LP87702 датащи(HTML) 62 Page - Texas Instruments |
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62 / 98 page  Table 7-36. PG0_FAULT Register Field Descriptions (continued) Bit Field Type Reset Description 0 PG0_FAULT_BUCK0 R 0h Source for PG0 inactive signal: 0 – Buck0 has not set PG0 signal inactive. 1 – Buck0 is selected for PG0 signal and it has set PG0 signal inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid. 7.6.1.1.27 PG1_CTRL Register (Offset = 1Ah) [reset = 0h] PG1_CTRL is shown in Figure 7-45 and described in Table 7-37. Return to Table 7-9. Figure 7-45. PG1_CTRL Register 7 6 5 4 3 2 1 0 PG1_RISE_DE LAY SEL_PG1_TWA RN SEL_PG1_VAN A SEL_PG1_VM ON2 SEL_PG1_VM ON1 SEL_PG1_BOO ST SEL_PG1_BUC K1 SEL_PG1_BUC K0 R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 7-37. PG1_CTRL Register Field Descriptions Bit Field Type Reset Description 7 PG1_RISE_DELAY R/W 0h 0 – PG1 rise is not delayed 1 – PG1 rise is delayed 11ms 6 SEL_PG1_TWARN R/W 0h PG1 control from thermal warning: 0 – Masked 1 – Affecting PGOOD (Default from OTP memory) 5 SEL_PG1_VANA R/W 0h PG1 signal source control from VANA 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 4 SEL_PG1_VMON2 R/W 0h PG1 signal source control from VMON2 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 3 SEL_PG1_VMON1 R/W 0h PG1 signal source control from VMON1 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 2 SEL_PG1_BOOST R/W 0h PG1 signal source control from Boost 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 1 SEL_PG1_BUCK1 R/W 0h PG1 signal source control from Buck1 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 0 SEL_PG1_BUCK0 R/W 0h PG1 signal source control from Buck0 0 – Masked 1 – Powergood threshold voltage (Default from OTP memory) 7.6.1.1.28 PG1_FAULT Register (Offset = 1Bh) [reset = 0h] PG1_FAULT is shown in Figure 7-46 and described in Table 7-38. Return to Table 7-9. LP87702 SNVSBU3 – MARCH 2021 www.ti.com 62 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702 |
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