PC97338VLJ datasheet(154/221 Pages) NSC

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RXD is accessed during CPU read cycles. It provides

the read data path from the receiver holding register

when the FIFOs are disabled, or from the RX_FIFO

bottom location when the FIFOs are enabled.

DMA cycles always access the transmitter and receiv-

er holding registers or FIFOs, regardless of the select-

ed bank.

5.14.2 IER – Interrupt Enable Register

This register controls the enabling of the various inter-

rupts. Some interrupts are common to all operating

modes, while others are only available with specific

modes. Bits 4 to 7 can be set in extended mode only.

They are cleared in non-extended mode. When a bit

is set to 1, an interrupt is generated when the corre-

sponding event occurs. In the non-extended mode

most events can be identified by reading the LSR and

MSR registers. The receiver high-data-level event

can only be identified by reading the EIR register after

the corresponding interrupt has been generated. In

the extended mode events are identified by event

flags in the EIR register. Upon reset, all bits are set to

Note 1: If the interrupt signal drives an edge-sensitive

interrupt controller input, it is advisable to disable all

interrupts by clearing all the IER bits upon entering

the interrupt routine, and re-enable them just before

exiting it. This will guarantee proper interrupt trigger-

ing in the interrupt controller in case one or more in-

terrupt events occur during execution of the interrupt

routine.If an interrupt source must be disabled, the

CPU can do so by clearing the corresponding bit in

the IER register. However, if an interrupt event occurs

just before the corresponding enable bit in the IER

ated. To avoid this problem, the clearing of any IER bit

should be done during execution of the interrupt ser-

vice routine.

Note 2: If the interrupt controller is programmed for

level-sensitive interrupts, the clearing of IER bits can

also be performed outside the interrupt service rou-

tine, but with the CPU interrupt disabled.

Note 3: If the LSR, MSR or EIR registers are to be

polled, the interrupt sources which are identified via

self-clearing bits should have their corresponding IER

bits set to 0. This will prevent spurious pulses on the

interrupt output pin.

FIGURE 88. Interrupt Enable Register

5.14.3 EIR/FCR – Event

Identification/FIFO Control

Registers

These registers share the same address.

EIR is accessed during CPU read cycles while FCR is

accessed during CPU write cycles.

EIR – Event Identification Register, Read-Only.

The function of this register changes depending upon

whether the module is in extended or non-extended

mode.

B0 RXHDL_IE – Receiver High-Data-Level Inter-

rupt Enable.

B1 TXLDL_IE – Transmitter Low-Data-Level Inter-

rupt Enable.

B2 UART, Sharp-IR, SIR Modes

LS_IE – Link Status Interrupt Enable.

MIR, FIR, CEIR Modes

LS_IE/TXHLT_IE – Link Status/Transmitter

Halted Interrupt Enable.

B3 MS_IE – Modem Status Interrupt Enable.

B4 DMA_IE – DMA Interrupt Enable.

B5 UART, Sharp-IR, CEIR Modes

TXEMP_IE – Transmitter Empty Interrupt En-

able.

SIR, MIR, FIR Modes

TXEMP_IE/PLD_IE – Transmitter Empty/Pipe-

line Load Interrupt Enable.

B6 MIR, FIR Modes

SFIF_IE – ST_FIFO Interrupt Enable.

B7 TMR_IE – Timer Interrupt Enable.

765

210

Reset

Required

LS_IE / TXHLT_IE

DMA_IE

TXEMP_IE/PLD_IE

SFIF_IE

TMR_IE

RXHDL_IE

TXLDL_IE

MS_IE

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