PC97338VLJ datasheet(38/221 Pages) NSC

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2.2.2

Software Device Configuration

Besides the three hardware-configured registers, all

Legacy-mode access to the configuration registers is

achieved by the use of an INDEX and DATA register

pair. Each configuration register is indicated by the

value loaded into the INDEX register. The data to be

written into or read from the indicated configuration

Accessing the configuration registers in this way re-

quires only two system I/O addresses. These two ad-

dresses are configured by strapping the values of pins

BADDR0 and BADDR1 during reset, as described in

Table 8. Since that I/O space is shared by other de-

vices the INDEX and DATA registers may conflict with

other system devices constrained to use this I/O ad-

dress space. Such conflicts may be resolved by

changing the INDEX and DATA register address as-

signments after reset, as described in Section 2.2.5.

TABLE 8. INDEX and DATA Register Address Op-

tions and Configuration Register Accessibility

2.2.3

Updating Configuration Registers

The settings of the configuration registers are acces-

sible via the INDEX and DATA registers. The location

of these registers is set by hardware during reset, and

the software is not informed of the chosen hardware

setting. The first step required to change configura-

tion registers settings is, to locate the addresses of

the INDEX and DATA registers.

To access the configuration registers after reset, use

the following procedure.

1. Determine the location of the INDEX register.

Check the possible locations (see Table 8) by

reading them twice. At the correct location only,

the first byte to return will be 88h, and the second

will be 00h. This double read must be conducted

before any writes have been made to the address-

es being checked since the ID byte is only issued

from the Index register during the first read after a

reset. (The register is reset by read. Subsequent

reads return the value loaded into the Index regis-

ter (except bits 6-4 which are reserved and always

read 0), or 00h if no write has been made).

2. Load the configuration registers.

A. Disable CPU interrupts (only for the PC87338).

B. Write the index of the configuration register

(00h-0Eh) to the INDEX register.

C. Write the correct data for the configuration reg-

ister to the DATA register (

one write access in

the PC97338 and two consecutive write ac-

cesses in the PC87338).

D. Enable CPU interrupts (only for the PC87338).

3. Load the configuration registers (read-modify-

write).

A. Disable CPU interrupts (only for the PC87338).

B. Write the index of the configuration register

(00h-0Eh) to the INDEX register.

C. Read the configuration data in that register via

the DATA register.

D. Modify the configuration data.

E. Write the changed data for the configuration reg-

ister to the DATA register (

one write access in

the PC97338 and two consecutive write ac-

cesses in the PC87338).

F. Enable CPU interrupts (only for the PC87338).

A single read access to the INDEX and DATA regis-

ters can be done at any time without disabling CPU in-

terrupts. Reading the INDEX register returns the last

value loaded into the INDEX register. Reading the

DATA register returns the configuration register data

pointed to by the INDEX register.

If during reset BADDR1 = 0 and BADDR0 = 1, the IN-

DEX and DATA register addresses are determined af-

ter reset via the Plug and Play protocol. As long as

these addresses are undefined, the configuration reg-

isters are not accessible. See Table 8.

2.2.4

Reserved Bits in Configuration

Registers

To maintain compatibility with future SuperI/O chips,

do not modify reserved bits when the register is writ-

ten, i.e., use read-modify-write to preserve the value

of reserved bits.

2.2.5

INDEX and DATA Register

Locations

During reset, the INDEX and DATA register pair can

be located at one of three locations by a hardware

strapping option on two pins (BADDR0 and BADDR1)

(see Table 8). This enables resolution of conflicts with

other devices in the I/O address space.

For all reset values of BADDR0,1, the INDEX and

DATA register pair can always be relocated via con-

figuration registers SBAL and SBAH. See “Relocating

the INDEX and DATA Register Pair” on page 40.

The INDEX register address is always even. The

DATA register is always at the next consecutive ad-

dress. Bit 7 of the INDEX register is reserved, and is

always read 0.

BADDR Pin

INDEX

Address

DATA

Address

Accessible

after Reset

398h

399h

Yes

undefined undefined

a. Apply Plug and Play protocol.

15Ch

15Dh

Yes

2Eh

2Fh

Yes

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