PC97338VLJ datasheet(150/221 Pages) NSC

150 / 221 page

150

www.national.com

The RC_MMD bits select the transmitter modulation

mode. If C_PLS mode is selected, modulation pulses

are generated continuously for the entire time in

which one or more logic 0 bits are being transmitted.

If 6_PLS or 8_PLS modes are selected, 6 or 8 pulses

are generated each time one or more logic 0 bits are

transmitted following a logic 1 bit. C_PLS modulation

mode is used for RC-5, RC-6, NEC and RCA proto-

cols. 8_PLS or 6_PLS modulation mode is used for

the RECS 80 protocol. The 8_PLS or 6_PLS mode al-

lows minimization of the number of bits needed to rep-

resent the RECS 80 infrared code sequence. The

current transmitter implementation supports only the

modulated modes of the RECS 80 protocol. The flash

mode is not supported since it is not popular and is

becoming less frequently used.

Note: The total transmission time for the logic 0 bits

must be equal or greater than 6 or 8 times the period

of the modulation subcarrier, otherwise fewer pulses

will be transmitted.

5.7.2

CEIR Receive Operation

The CEIR receiver is significantly different from a

UART receiver for two basic reasons. First, the in-

coming infrared signals are DASK modulated. There-

fore, a demodulation operation may be necessary.

Second, there are no start bits in the incoming data

stream.

Whenever an infrared signal is detected, the opera-

tions performed by the receiver are slightly different

depending on whether or not receiver demodulation is

enabled. If the demodulator is not enabled, the receiv-

er will immediately switch to the active state. If the de-

modulator is enabled, the receiver checks the

subcarrier frequency of the incoming signal, and it

switches to the active state only if the frequency falls

within the programmed range. If this is not the case,

the signal is ignored and no other action is taken.

When the receiver active state is entered, the RXACT

bit in the ASCR register is set to 1. Once in the active

state, the receiver keeps sampling the infrared input

signal and generates a bit stream where a logic 1 in-

dicates an idle condition and a logic 0 indicates the

presence of infrared energy. The infrared input is

sampled regardless of the presence of infrared pulses

at a rate determined by the value loaded into the baud

generator divisor register. The received bit string is ei-

ther de-serialized and assembled into 8-bit charac-

ters, or it is converted to run-length encoding values.

The resulting data bytes are then transferred to the

RX_FIFO.

The receiver also sets the RXWDG bit in the ASCR

This bit is automatically cleared when the ASCR reg-

ister is read, and it is intended to assist the software

in determining when the infrared link has been idle for

a certain time. The software can then stop the data re-

ception by writing a 1 into the RXACT bit to clear it and

return the receiver to the inactive state.

The frequency bandwidth for the incoming modulated

infrared signal is selected by DFR and DBW bits in the

IRRXDC register. There are two CEIR receiver data

modes: “Over-sampled” and “Programmed-T-Period”

mode. For either mode the sampling rate is deter-

mined by the setting of the baud generator divisor reg-

ister.

The “Over-sampled” mode can be used with the re-

ceiver demodulator either enabled or disabled. It

should be used with the demodulator disabled when

a detailed snapshot of the incoming signal is needed,

for example to determine the period of the subcarrier

signal. If the demodulator is enabled, the stream of

samples can be used to reconstruct the incoming bit

string. To obtain a good resolution, a fairly high sam-

pling rate should be selected.

The “Programmed-T-Period” mode should be used

with the receiver demodulator enabled. The T Period

represents one half bit time, for protocols using bi-

phase encoding, or the basic unit of pulse distance,

for protocols using pulse distance encoding. The

baud rate is usually programmed to match the T Peri-

od. For long periods of logic low or high, the receiver

samples the demodulated signal at the programmed

sampling rate.

Whenever a new infrared energy pulse is detected,

the receiver will re-synchronize the sampling process

to the incoming signal timing. This reduces timing re-

lated errors and eliminates the possibility of missing

short infrared pulse sequences, especially when deal-

ing with the RECS 80 protocol. In addition, the “Pro-

grammed-T-Period” sampling minimizes the amount

of data used to represent the incoming infrared signal,

therefore reducing the processing overhead in the

host CPU.

5.8

FIFO TIME-OUTS

In order to prevent received data from sitting in the

RX_FIFO and/or the ST_FIFO indefinitely, if the pro-

grammed interrupt or DMA thresholds are not

reached, time-out mechanisms are provided.

An RX_FIFO time-out generates a receiver High-

Data-Level interrupt and/or a Receiver DMA request

if bit 0 of IER and/or bit 2 of MCR (in extended mode)

are set to 1 respectively. An RX_FIFO time-out also

sets bit 0 of ASCR to 1 if the RX_FIFO is below the

threshold. This bit is tested by the software, when a

PC97338VLJ датащи(PDF) 150 Page - National Semiconductor (TI)

PC97338VLJ датащи(HTML) 150 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL