PC97338VLJ datasheet(55/221 Pages) NSC

55 / 221 page

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2.3.15 Chip Select 0 High Address

This register holds the high address bits of the moni-

tored I/O address. See CS0LA and CS0CF for com-

plementary description. Bit 0 holds A8. If during reset

CFG0 is1, A15-11 are not input signals of the chip.

Therefore, bits 7-3 are reserved.

FIGURE 16. CS0HA Register Bitmap

2.3.16 Chip Select 1 High Address

This register holds the high address bits of the moni-

tored I/O address. See CS1LA and CS1CF for com-

plementary description. Bit 0 holds A8. If during reset

CFG0 is 1, A15-11 are not input pins of the chip.

Therefore, bits 7-3 are reserved.

FIGURE 17. CS1HA Register Bitmap

2.3.17 SuperI/O Chip Configuration

Upon reset, SCF0 is initialized to xxxx0xxx.

FIGURE 18. SCF0 Register Bitmap

Bits 2-0 - Reserved

These bits are reserved.

Bit 3 - SCC2 TRI-STATE Control

This bit controls the TRI-STATE status of the

SCC2 output pins and blocked the input pins, to

avoid leakage current. This bit does not control the

TRI-STATE status of the SCC2 interrupt.

0 - No TRI-STATE enabled in SCC2 pins.

1 - If SCC2 is disabled or the Chip is in power-

down mode, SCC2 and IR output signals are

in TRI-STATE and the input signals are

blocked to reduce their leakage current.

The values of the blocked input signals are:

IRRX1=1,

IRRX2=1,

SIN2=1,

CTS2=1,

DSR2=1, DCD2=1, ID0=1, ID1=1, ID2=1 and

RI2=1.

When IRSL2-0 control their respective pins

they are all 0, under these conditions.

Bits 7-4 - Reserved

Reserved.

A10

A11

A12

A13

A14

A15

Reserved

A10

Reserved

Address Length

543

(CS0HA)

Reset

Required

Chip Select 0

Index 10h

High Address Register

11 Bits

16 bits

CFG0 = 1

CFG0 = 0

A10

A11

A12

A13

A14

A15

Reserved

A10

Reserved

Address Length

543

(CS1HA)

Reset

Required

Chip Select 1

Index 11h

High Address Register

11 Bits

16 bits

CFG0 = 1

CFG0 = 0

543

Reset

Required

Index 12h

SuperI/O Chip

Reserved

SCC2 TRI-STATE Control

Reserved

Configuration

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