PC97338VLJ datasheet(151/221 Pages) NSC

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receiver High-Data-Level interrupt occurs, to decide

whether a number of bytes, as indicated by the

RX_FIFO threshold, can be read without checking bit

0 of the LSR register. An ST_FIFO time-out is en-

abled only in MIR and FIR modes, and generates an

interrupt if bit 6 of IER is set to 1.

The conditions that must exist for a time-out to occur

in the various modes of operation, are described be-

low. When a time-out has occurred, it can only be re-

set when the FIFO that caused the time-out is read by

the CPU or DMA controller.

MIR or FIR Modes

RX_FIFO Time-out Conditions:

1. At least one byte is in the RX_FIFO, and

2. More than 64

µs have elapsed since the last byte

was loaded into the RX_FIFO from the receiver

logic, and

3. More than 64

µs have elapsed since the last byte

was read from the RX_FIFO by the CPU or DMA

controller.

ST_FIFO Time-out Conditions:

1. At least one entry is in the ST_FIFO, and

2. More than 1 ms has elapsed since the last byte

was loaded into the RX_FIFO by the receiver log-

ic, and

3. More than 1 ms has elapsed since the last entry

was read from the ST_FIFO by the CPU.

UART, Sharp-IR, SIR Modes

RX_FIFO Time-out Conditions:

1. At least one byte is in the RX_FIFO, and

2. More than four character times have elapsed since

the last byte was loaded into the RX_FIFO from

the receiver logic, and

3. More than four character times have elapsed since

the last byte was read from the RX_FIFO by the

CPU or DMA controller.

CEIR Mode

RX_FIFO Time-out Conditions:

The RX_FIFO Time-out, in CEIR mode, is disabled

while the receiver is active. The conditions for this

time-out to occur are as follows:

1. At least one byte has been in the RX_FIFO for 64

µs or more, and

2. The receiver has been inactive (RXACT=0) for 64

µs or more, and

3. More than 64

µs have elapsed since the last byte

was read from the RX_FIFO by the CPU or DMA

controller.

5.9

TRANSMIT DEFERRAL

This feature allows the software to send short high-

speed data frames in PIO mode without the risk of a

transmitter underrun being generated. Even though

this feature is available and works the same way in all

modes, it will most likely be used in MIR and FIR

modes to support high-speed negotiations. This is be-

cause in other modes, either the transmit data rate is

relatively low and thus the CPU can keep up with it

without letting an underrun occur, as in the case CEIR

Mode, or transmit underruns are allowed and are not

considered to be error conditions.

Transmit deferral is available only in extended mode

and when the TX_FIFO is enabled. When transmit de-

ferral is enabled (TX_DFR bit of MCR set to 1) and the

transmitter becomes empty, an internal flag will be set

that locks the transmitter. If the CPU now writes data

into the TX_FIFO, the transmitter will not start sending

the data until the TX_FIFO level reaches either 14 for

a 16-level TX_FIFO, or 30 for a 32-level TX_FIFO, at

which time the internal flag is cleared. The internal

flag is also cleared and the transmitter starts transmit-

ting when a time-out condition is reached. This pre-

vents some bytes from being in the TX_FIFO

indefinitely if the threshold is not reached.

The time-out mechanism is implemented by a timer

that is enabled when the internal flag is set and there

is at least one byte in the TX_FIFO. Whenever a byte

is loaded into the TX_FIFO the timer gets reloaded

with the initial value. If no bytes are loaded for a 64-s

time, the timer times out and the internal flag gets

cleared, thus enabling the transmitter.

5.10 AUTOMATIC FALLBACK TO 16550

COMPATIBILITY MODE

This feature is designed to support existing legacy

software packages using the 16550 UART.

For proper operation, many of these software packag-

es require that the module look identical to a plain

16550 since they access the UART registers directly.

Due to the fact that several extended features as well

as new operational modes are provided, the user

must make sure that the module is in the proper state

before a legacy program can be executed.

The fallback mechanism is designed for this purpose.

It eliminates the need for user intervention to change

the state of the module, when a legacy program must

be executed following completion of a program that

used any of the module's extended features.

This mechanism automatically switches the module

to 16550 compatibility mode and turns off any extend-

ed features whenever the baud generator divisor reg-

ister is accessed through the LBGD(L) or LBGD(H)

ports in register bank 1.

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