PC97338VLJ datasheet(82/221 Pages) NSC

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3.3.7

Data Rate Select Register (DSR),

Offset 100

This write-only register is used to program the data

transfer rate, amount of write precompensation, pow-

er down mode, and software reset.

The data transfer rate is programmed via the CCR,

not the DSR, for PC-AT, PS/2 and Micro Channel ap-

plications. Other applications can set the data transfer

rate in the DSR.

The data rate of the floppy controller is determined by

the most recent write to either the DSR or CCR.

The DSR is unaffected by a software reset. A hard-

ware reset sets the DSR to 02h, which corresponds to

the default precompensation setting and a data trans-

fer rate of 250 Kbps.

FIGURE 50. DSR Register Bitmap

Bits 1,0 - Data Transfer Rate Select 1,0

(DRATE 1,0)

These bits determine the data transfer rate for the

Floppy Disk Controller (FDC), depending on the

supported speeds. See “Tape, SCCs and Parallel

Port Configuration Register (TUP), Index 07h” on

page 51. Table 40 shows the data transfer rate se-

lected by each value of this field.

These bits are unaffected by a software reset, and

are set to 10 (250 Kbps) after a hardware reset.

TABLE 40. Data Transfer Rate Encoding

Bits 4-2 - Precompensation Delay Select

This field sets the write precompensation delay

that the Floppy Disk Controller (FDC) imposes on

the WDATA disk interface output signal, depend-

ing on the supported speeds. See “Tape, SCCs

and Parallel Port Configuration Register (TUP),

Index 07h” on page 51. Table 3-6 shows the delay

for each value of this field.

In most cases, the default delays shown in Table

42 are adequate. However, alternate values may

be used for specific drive and media types.

Track 0 is the default starting track number for pre-

compensation. The starting track number can be

changed using the CONFIGURE command.

TABLE 41. Write Precompensation Delays

TABLE 42. Default Precompensation Delays

Bit 5 - Undefined

Should be set to 0.

Bit 6 - Low Power

This bit triggers a manual power down of the FDC

in which the clock and data separator circuits are

turned off. A manual power down can also be trig-

gered by the MODE command.

After a manual power down, the FDC returns to

normal power after a software reset, or an access

to the Data Register (FIFO) or the Main Status

DSR Bits

(DRATE)

Value of Bit 1 of TUP

0 (24 MHz)

1 (48 MHz)

500 Kbps

Invalid

300 Kbps

Invalid

250 Kbps

Invalid

1 Mbps

2 Mbpsa

a. Not 100% tested.

321

Reset

Required

Data Rate Select

Offset 100

Precompensation Delay Select

Undefined

Low Power

Software Reset

DRATE1

DRATE0

DSR Bits

Value of Bit 1 of TUP

0 (24 MHz)

1 (48 MHz)

Default (Table 42)

41.7 nsec

20.8 nsec

83.3 nsec

41.7 nsec

125.0 nsec

62.5 nsec

166.7 nsec

83.3 nsec

208.3 nsec

104.2 nsec

250.0 nsec

125.0 nsec

0.0 nsec

Data Rate

Precompensation Delay

2 Mbps

20.8 nsec

1 Mbps

41.7 nsec

500 Kbps

125.0 nsec

300 Kbps

125.0 nsec

250 Kbps

125.0 nsec

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