PC97338VLJ datasheet(158/221 Pages) NSC

158 / 221 page

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Bits 0 to 6 are only effective in UART, Sharp-IR and

SIR modes.

They are ignored in MIR, FIR and CEIR modes.

FIGURE 88. Link Control Register

TABLE 78. Word Length Select Encoding

TABLE 79. Bit Settings for Parity Control

B1–0 WLS [1–0] – Character Length.

These bits specify the length of each transmit-

ted or received serial character.

Bits 1-0

Character Length

5 Bits(Default)

6 Bits

7 Bits

8 Bits

B2 STB – Stop Bits.

Number of stop bits in each transmitted serial

character. If this bit is 0, 1 stop bit is generated in

the transmitted data. If it is 1 and a 5-bit character

length is selected via bits 0 and 1, 1.5 stop bits are

generated. If it is 1 and a 6, 7 or 8-bit character

length is selected, 2 stop bits are generated. The

receiver checks 1 stop bit only, regardless of the

number of stop bits selected.

B3 PEN – Parity Enable.

When set to 1, parity bits are generated and

checked by the transmitter and receiver channels

respectively.

B4 EPS – Even Parity.

Used in conjunction with the STKP bit to deter-

mine the parity bit. See encodings below.

B5 STKP – Stick Parity.

The encodings of this and the previous two bits,

for control of the parity bit, are as follows:

543

Reset

Required

STB

EPS

STKP

SBRK

BKSE

WLS0

WLS1

PEN

EPS

STKP

Selected Parity

None

100

Odd

110

Even

101

Logic 1

111

Logic 0

B6 SBRK – Set Break.

When set to 1, the following occurs:

—

If UART mode is selected, the SOUT pin is forced

to a logic 0 state.

—

If SIR mode is selected, pulses are issued contin-

uously on the IRTX pin.

—

If Sharp-IR mode is selected and internal modu-

lation is enabled, pulses are issued continuously

on the IRTX pin.

—

If Sharp-IR mode is selected and internal modu-

lation is disabled, the IRTX pin is forced to a logic

1 state.

The break is disabled by setting this bit to 0. This

bit acts only on the transmitter front-end and has

no effect on the rest of the transmitter logic.

The following sequence should be followed to

avoid transmission of erroneous characters be-

cause of the break.

1. Wait for the transmitter to be empty (TXEMP =

1).

2. Set SBRK to 1.

3. Wait for the transmitter to be empty, and clear

SBRK when normal transmission has to be re-

stored.

During the break, the transmitter can be used as

a character timer to accurately establish the

break duration.

B7 BKSE – Bank Select Enable.

In the LCR register this bit is always 0.

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