PC97338VLJ datasheet(66/221 Pages) NSC

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TABLE 31. SIRQI3 Plug and Play Interrupt Map-

ping

Bit 4 - Invert SIRQI3

In the following, x = 3, 4, 5, 6, 7, 9, 10, 11, 12 or

15, according to bits 0-3 of this register.

0 - SIRQI3 not inverted. IRQx = SIRQI3.

1 - SIRQI3 inverted. IRQx = SIRQI3.

Bit 5 - SIRQI3 Status

This bit is read-only. It holds the value of SIRQI3,

when selected on the pin.

Bits 7,6 - Select DRV2, DR23, PNF or SIRQI3

When DR23 controls the pin, it is asserted when

either drive 2 or drive 3 is accessed (except during

logical drive exchange - see bit 3 of TDR). Its value

is undefined in four drive encoded mode, i.e.,

when bit 4 of the FER register is 1.

DRV2 is masked to 1, when DR23 controls the pin

on the pin. When DRV2, PNF or SIRQI3 control

the pin, the pin is read via the DRV2 bit (in the FDC

registers).

When PNF does not control the pin, it is masked to

These bits are ignored when bit 1 of the SCF3 reg-

ister is 1. Bit 1 of the SCF3 register allows selec-

tion of IRSL2/

ID0 (ID0 in PC97338 only) to control

the pin.

Table 32 shows how the values of these bits con-

trol which signal uses the pin they share.

TABLE 32. SelectingDRV2,DR23, PNF orSIRQI3

2.3.36 Plug-and-Play Configuration 3

This register allows configurable mapping of the

SCC2 DMA signals onto the ISA DMA channels, as

shown in Tables 33 and 34, for reception and trans-

mission, respectively.

When a DMA request pin, i.e., DRQ0, DRQ1, DRQ2

or DRQ3, is not configured as an FDC DMA request

signal, a parallel port DMA request signal or a SCC2

DMA request signal, it is in TRI-STATE.

When a DMA acknowledge pin, i.e., DACK0, DACK1,

DACK2 or DACK3, is not configured as an FDC DMA

acknowledge signal, a parallel port DMA acknowl-

edge signal or a SCC2 DMA acknowledge signal, it is

ignored.

FIGURE 38. PNP3 Register Bitmap

Bit 3Bit 2Bit 1

Bit 0

Interrupt

000

Disable

000

Invalid

001

Invalid

001

IRQ3

010

IRQ4

010

IRQ5

011

IRQ6

011

IRQ7

100

Invalid

100

IRQ9

101

IRQ10

101

IRQ11

110

IRQ12

110

Invalid

111

Invalid

111

IRQ15

Bit 1 of

SCF3

Bit 7 of

SIRQ3

Bit 6 of

SIRQ3

Signal that Uses

the Pin

DRV2

DR23

PNF

SIRQI3

IRSL2

SCC2 DMA

SCC2 DMA Plug and Play

Reserved

543

Reset

Required

(PNP3)

Plug and Play Configuration

Index 4Fh

Plug and Play Support

for Reception

Reserved

Support for Transmission

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