PC97338VLJ datasheet(152/221 Pages) NSC

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In order to avoid spurious fallbacks, baud generator

divisor ports are provided in bank 2. Accesses of the

baud generator divisor through these ports will

change the baud rate setting but will not cause a fall

back.

New programs, designed to take advantage of the ex-

tended features, should not use LBGD(L) and LB-

GD(H) to change the baud rate. They should use

BGD(L) and BGD(H) instead.

A fallback can occur from either extended or non-ex-

tended modes. If extended mode is selected, fallback

is always enabled. In this case, when a fallback oc-

curs, the following happens:

1. Transmitter and receiver FIFOs will switch to 16

levels.

2. A value of 13 will be selected for the baud genera-

tor prescaler.

3. The ETDLBK and BTEST bits in the EXCR1 Reg-

ister will be cleared.

4. UART mode will be selected.

5. A switch to non-extended mode will occur.

When a fallback occurs from non-extended mode,

only the first three of the above actions will take place.

No switching to UART mode occurs if either Sharp_IR

or SIR infrared modes were selected. This prevents

spurious switchings to UART mode when a legacy

program, running in infrared mode, accesses the

baud generator divisor register from bank 1.

Fallback from non-extended mode can be disabled by

setting the LOCK bit in the EXCR2 register. When

Lock is set to 1 and the module is in non-extended

mode, two scratchpad registers overlayed with LB-

GD(L) and LBGD(H) are enabled. Any attempted

CPU access of the baud generator divisor register

through LBGD(L) and LBGD(H) will access the

scratchpad registers, and the baud rate setting will not

be affected. This feature allows existing legacy pro-

grams to run faster than 115.2 kbaud without their be-

ing aware of it.

5.11 PIPELINING

This feature is designed to support the IrDA infrared

modes and it allows minimization of the time delay

from the end of a negotiation phase to the subsequent

data transfer phase.

The module accomplishes this objective by automati-

cally selecting a new mode and/or loading new values

into the baud generator divisor register as soon as the

current data transmission completes and the trans-

mitter becomes empty. The new operational mode

and the baud divisor value are programmed into spe-

cial pipeline registers.

Pipelining is automatically disabled after a pipeline

operation takes place. It should be re-enabled by the

software after the special pipeline registers have

been reloaded.

Even though there are no other restrictions between

source and target modes, aside from having to be

IrDA modes, pipelining will most likely be used from

SIR as the source mode, since SIR is the mode used

by the negotiation procedures in the presently defined

IrDA protocols.

Following a pipeline operation, the transmitter will be

halted for 250

µs to allow the newly selected receive

filter in the remote optical transceiver to stabilize. If a

switch from either MIR or FIR to SIR occurred as a re-

sult of pipelining, the transmitter will be halted for 250

µs or a character time (at the newly selected baud

rate), whichever is greater. This is to guarantee that

reception at a remote station of any character trig-

gered by an interaction pulse is complete before the

next SIR data transmission begins.

Since a pipelining operation is performed without soft-

ware intervention, automatic transceiver configuration

must be enabled.

5.12 OPTICAL TRANSCEIVER

INTERFACE

The PC97338 implements a very flexible interface for

the external infrared transceiver. Several signals are

provided for this purpose. A transceiver module with

one or two receive signals, or two transceiver mod-

ules can be directly interfaced without any additional

logic.

Since various operational modes are supported, the

transmitter power as well as the receiver filter in the

transceiver module must be configured according to

the selected mode.

The PC97338 provides three special interface pins

ID/IRSL[2–0] to control the infrared transceiver. The

logic levels of the ID/IRSL[2–0] pins can be either di-

rectly controlled by the software (through the setting

of bits 2–0 in the IRCFG1 register), or can be auto-

matically selected by the module whenever a new

mode is entered.

The automatic transceiver configuration is enabled by

setting the AMCFG bit in the IRCFG4 register to 1.

One of its advantages is that it allows the low-level

functional details of the transceiver module being

used to be hidden from the software drivers. It also

speeds up the transceiver mode selection, and it must

be enabled if the pipelining feature is to be used.

The operational mode settings for the automatic con-

figuration are determined by various bit fields in the

IRCFGn registers that must be programmed when the

module is initialized.

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