PC97338VLJ datasheet(26/221 Pages) NSC

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DRATE0

DRATE1

(Normal

Mode)

Group 8

Data Rates 0 and 1. These FDC output signals reflect the currently

selected FDC data rate, (bits 1 and 0 in the Configuration Control

was written to last). The pins are totem-pole buffered output signals

(6 mA sink, 6 mA source).

DRATE0 is multiplexed with MSEN0. DRATE1 is multiplexed with

MSEN1, SIRQI2, CS0 and DACK3.

DRATE0

(PPM

Mode)

Group 8

Data Rate 0. This pin provides an additional FDC data rate signal,

in PPM mode, when PNF = 0.

DRATE0 is multiplexed with PD6. See Table 72 for more

information.

DRQ0

DRQ1

DRQ2

DRQ3

Group 6

DMA Requests 0, 1, 2 and 3. These active high outputs signal the

DMA controller that a data transfer is required.

This DMA request can be sourced by one of the following: FDC,

SCC2 or parallel port. When not sourced by any of them, it is in

TRI-STATE. In Plug and Play mode, when the sourced device is

disabled or when the sourced device is configured with no DMA, it

is also in TRI-STATE. Upon reset, DRQ2 is used by the FDC; and

DRQ0,1 and 3 are in TRI-STATE.

DRQ3 is multiplexed with IRQ15, and SIRQI1.

DRV2

Group 4

Drive2. This FDC input signal indicates (low) when a second disk

drive has been installed. The state of this signal is available from

Status Register A in PS/2 mode. This pin is configured when bits 7

and 6 of SIRQ3 are 00.

DRV2 is multiplexed with DR23, PNF, SIRQI3 and IRSL2.

DSKCHG

(Normal

Mode)

Group 4

Disk Change. This FDC input signal indicates if the drive door is

open. The state of this signal is available from the Digital Input

data separator diagnostic input signal via the MODE command (see

“The MODE Command” on page -101)

(PPM

Mode)

Group 4

Disk Change. This signal provides an additional FDC Disk Change

signal in PPM Mode when PNF = 0.DSKCHG is multiplexed with

PD4. See Table 36 for more information.

DSR1

DSR2

Group 1

Data Set Ready signals 1 and 2. When low, these UART signals

indicates that the appropriate data transfer device or modem is

ready to establish a communications link. The DSR signal is a

modem status input whose condition can be tested by reading bit 5

(DSR) of the Modem Status Register (MSR) for the appropriate

channel. Bit 5 is the complement of the DSR signal. Bit 1 (DDSR)

of the MSR indicates whether the DSR input signal has changed

state since the previous reading of the MSR.

If modem status interrupts are enabled an interrupt is generated

whenever the DDSR bit of the MSR is set.

When DSR2 is not selected, it is masked to 0.

DSR2 is multiplexed with IRRX2, IRQ12 and IRSL0.

DSTRB

Group 11

Data Strobe. This signal is used in EPP mode as a data strobe. It

is active low.

DSTRB is multiplexed with AFD, DENSEL. See Table 72 for more

information.

Symbol

PQFP

TQFP

I/O and

Group #

Function

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