PC97338VLJ datasheet(153/221 Pages) NSC

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The ID/IR_SL[2–0] pins will power up as inputs and

can be driven by an external source. When in input

mode, they can be used to read the identification data

of Plug-n-Play infrared adapters.

The ID0/IRSL0/IRRX2 pin can also function as an in-

put to support an additional infrared receive signal. In

this case, however, only two configuration pins will be

available. The IRSL0_DS and IRSL21_DS bits in the

IRCFG4 register determine the direction of the

ID/IRSL[2–0] pins.

5.13 ARCHITECTURAL DESCRIPTION

Eight register banks are provided to control the oper-

ation of the UIR module. These banks are mapped

into the same address range, and only the selected

bank is directly accessible by the software. The ad-

dress range spans 8 byte locations. The BSR register

is used to select the bank and is common to all banks.

Therefore, each bank defines seven new registers.

The register banks can be divided into two sets.

Banks 0–3 are used to control both UART and infra-

red modes of operation; banks 4–7 are used to control

and configure the infrared modes only. The register

bank main functions are listed in Table 73. Descrip-

tions of the various registers are given in the following

sections.

FIGURE 88. Register Bank Architecture

TABLE 73. Register Bank Summary

5.14 BANK 0

TABLE 74. Bank 0 Serial Controller Base Regis-

ters þ

5.14.1 TXD/RXD – Transmit/Receive Data

Ports

These ports share the same address.

TXD is accessed during CPU write cycles. It provides

the write data path to the transmitter holding register

when the FIFOs are disabled, or to the TX_FIFO top

location when the FIFOs are enabled.

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

Offset 07h

Offset 06h

Offset 05h

Offset 04h

LCR/BSR

Offset 02h

Offset 01h

Offset 00h

Common

Throughout

All Banks

16550 Banks

Bank

UART

Mode

Description

Global Control and Status

Registers

Legacy Bank

Baud Generator Divisor and

Extended Control

Identification and Shadow

Registers

Timer and Counters

Infrared Control and Status

FIFO

Infrared Physical Layer

Configuration

CEIR and Optical

Transceiver Configuration

Address

Offset

Name

Description

00h

TXD/

RXD

Transmitter/Receiver Data Ports

01h

IER

Interrupt Enable Register

02h

EIR/

FCR

Event Identification/

FIFO Control Registers

03h

LCR/

BSR

Link Control/Bank Select

Registers

04h

MCR

Modem/Mode Control Register

05h

LSR

Link Status Register

06h

MSR

Modem Status Register

07h

SPR/

ASCR

Scratchpad/ Auxiliary Status

and Control Registers

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