PC97338VLJ datasheet(156/221 Pages) NSC

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FIGURE 88. Event Identification Register,

Extended Mode

B0 RXHDLEV – Receiver High-Data-Level Event.

FIFOs Disabled: Set to 1 when one character is in

the receiver holding register.

FIFOs Enabled: Set to 1 when the RX_FIFO level

is equal to or above the threshold level, or an

RX_FIFO time-out has occurred.

B1 TXLDL_EV

–

Transmitter

Low-Data-Level

Event.

FIFOs Disabled: Set to 1 when the transmitter

holding register is empty.

FIFOs Enabled: Set to 1 when the TX_FIFO level

is below the threshold level.

UART, Sharp-IR, SIR Modes

LS_EV – Link Status Event.

Set to 1 when a receiver error or break condition

is reported.

Note that, when the FIFOs are enabled, the PE,

FE and BRK conditions are only reported when

the associated character reaches the bottom of

the RX_FIFO. An overrun error (OE) is reported

as soon as it occurs.

MIR, FIR Modes

LS_EV/TX_HLT_EV – Link Status/Transmitter

Halted Event.

Set to 1 when any of the following conditions oc-

cur:

1. Last byte of received frame reaches the bottom

of the RX_FIFO

2. Receiver overrun

3. Transmitter underrun

4. Transmitted halted on frame end CEIR Mode

Consumer_IR Mode

LS_EV/TXHLT_EV – Link Status/Transmitter

Halted.

Set to 1 when a receiver overrun or a transmitter

underrun condition occurs.

765

210

Reset

Required

DMA_EV

TXXEMP_EV/PPLD_EV

SFIF_EV

TMR_EV

RXHDL_EV

TXLDL_EV

MS_EV

LS_EV/TX_HLT_EV

Note: A high speed CPU can service the interrupt

generated by the last frame byte reaching the

RX_FIFO bottom before that byte is transferred to

memory by the DMA controller. This can happen

when the CPU interrupt latency is shorter than the

RX_FIFO Time-out (Refer to the “FIFO Time-

outs” section). A DMA request is generated only

when the RX_FIFO level reaches the DMA

threshold or when a FIFO time-out occurs, in or-

der to minimize the performance degradation due

to DMA signal handshake sequences. If the DMA

controller must be set up before receiving each

frame, the software in the interrupt routine should

make sure that the last byte of the frame just re-

ceived has been transferred to memory before re-

initializing the DMA controller, otherwise that byte

could appear as the first byte of the next received

frame.

UART Mode

MS_EV – Modem Status Event.

Set to 1 when any of the bits 0 to 3 in the MSR

Any Infrared Mode

MS_EV/Unused – Modem Status Event.

The function of this bit depends on the setting of

the IRMSSL bit in the IRCR2 register.

ISMSSL Value

Bit Function

Modem Status interrupt event

Forced to 0

B4 DMA_EV – DMA Event.

When an 8237 type DMA controller is used, this

bit is set to 1 when a DMA terminal count (TC) is

signaled. It is cleared upon read.

B5 UART, Sharp-IR, CEIR Modes

TXEMP_EV – Transmitter Empty.

This bit is the same as bit 6 of the LSR register.

It is set to 1 when the transmitter is empty.

MIR, FIR, SIR Modes

TXEMPEV/PLDEV – Transmitter Empty/Pipe-

line Load Event.

Set to 1 when the transmitter is empty or a pipe-

line operation occurs.

MIR, FIR Modes

SFIF_EV – ST_FIFO Event.

Set to 1 when the ST_FIFO level is equal to or

above the threshold, or an ST_FIFO time-out oc-

curs. This bit is cleared when the CPU reads the

ST_FIFO and its level drops below the threshold.

B7 TMR_EV – Timer Event.

Set to 1 when the timer reaches 0.

Cleared by writing 1 into bit 7 of the ASCR regis-

ter.

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