PC97338VLJ datasheet(149/221 Pages) NSC

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5.6.2

High Speed Infrared Receive

Operation

When the receiver front-end detects an incoming

frame, it will start de-serializing the infrared bit stream

and load the resulting data bytes into the RX_FIFO.

When the EOF is detected, two or four CRC bytes are

appended to the received data, and an EOF flag is

written into the tag section of the RX_FIFO along with

the last byte. In the present implementation, the CRC

bytes are always transferred to the RX_FIFO follow-

ing the data. Additional status information, related to

the received frame, is also written into the RX_FIFO

tag section at this time. The status information will be

loaded into the LSR register when the last frame byte

reaches the RX_FIFO bottom.

The receiver keeps track of the number of received

bytes from the beginning of the current frame. It will

only transfer to the RX_FIFO a number of bytes not

exceeding the maximum frame length value which is

programmed via the RFRML register in bank 4. Any

additional frame bytes will be discarded. When the

maximum frame length value is exceeded, the

MAX_LEN error flag will be set.

Although data transfers from the RX_FIFO to memory

can be performed either in PIO or DMA mode, DMA

mode should be used due to the high data rates.

In order to handle back-to-back incoming frames,

when DMA mode is selected and an 8237 type DMA

controller is used, an 8-level ST_FIFO (Status FIFO)

is provided. When an EOF is detected, in 8237 DMA

mode, the status and byte count information for the

frame is written into the ST_FIFO. An interrupt is gen-

erated when the ST_FIFO level reaches a pro-

grammed threshold or an ST_FIFO time-out occurs.

The CPU uses this information to locate the frame

boundaries in the memory buffer where the data, be-

longing to the received frames, has been transferred

by the 8237 type DMA controller.

During reception of multiple frames, if the RX_FIFO

and/or the ST_FIFO fills up, due to the DMA controller

or CPU not serving them in time, one or more frames

can be crushed and lost. This means that no bytes be-

longing to these frames were written to the RX_FIFO.

In fact, a frame will be lost in 8237 mode when the

ST_FIFO is full for the entire time during which the

frame is being received, even though there were emp-

ty locations in the RX_FIFO. This is because no data

bytes can be loaded into the RX_FIFO and then trans-

ferred to memory by the DMA controller, unless there

is at least one available entry in the ST_FIFO to store

the number of received bytes. This information, as

mentioned before, is needed by the software to locate

the frame boundaries in the DMA memory buffer.

In the event that a number of frames are lost, for any

of the reasons mentioned above, one or more lost-

frame indications including the number of lost frames,

are loaded into the ST_FIFO.

Frames can also be lost in PIO mode, but only when

the RX_FIFO is full. The reason being that, in these

cases, the ST_FIFO is only used to store lost-frame

indications. It will not store frame status and byte

count.

5.7

CONSUMER ELECTRONIC IR

(CEIR) MODE

The CEIR circuitry is designed to optimally support all

the major protocols presently used in remote-con-

trolled home entertainment equipment. The main pro-

tocols currently in use are: RC-5, RC-6, RECS 80,

NEC and RCA. The PC87108, in conjunction with an

external optical module, provides the physical layer

functions necessary to support these protocols.

These functions include modulation, demodulation,

serialization, de-serialization, data buffering, status

reporting, interrupt generation, etc. The software is re-

sponsible for the generation of the infrared code to be

transmitted, and for the interpretation of the received

code.

5.7.1

CEIR Transmit Operation

The code to be transmitted consists of a sequence of

bytes that represent either a bit string or a set of run-

length codes. The number of bits or run-length codes

usually needed to represent each infrared code bit de-

pends on the infrared protocol used. The RC-5 proto-

col, for example, needs two bits or between one and

two run-length codes to represent each infrared code

bit.

CEIR transmission starts when the transmitter is emp-

ty and either the CPU or the DMA controller writes

code bytes into the TX_FIFO. The transmission is

normally completed when the CPU sets the S_EOT

bit in the ASCR register before writing the last byte, or

when the DMA controller activates the TC signal.

Transmission is also completed if the CPU simply

stops transferring data and the transmitter becomes

empty. In this case however, a transmitter underrun

condition will be generated. The underrun must be

cleared before the next transmission can occur. The

code bytes written into the TX_FIFO are either de-se-

rialized or run-length decoded, and the resulting bit

string is modulated by a subcarrier signal and sent to

the transmitter LED. The bit rate of this bit string, like

in the UART mode, is determined by the value pro-

grammed in the baud generator divisor register. Un-

like a UART transmission, start, stop and parity bits

are not included in the transmitted data stream. A log-

ic 1 in the bit string will keep the LED off, so no infra-

red signal is transmitted. A logic 0 will generate a

sequence of modulating pulses which will turn on the

transmitter LED. Frequency and pulse width of the

modulating pulses are programmed by the MCFR and

MCPW bits in the IRTXMC register as well as the

TXHSC bit in the RCCFG register.

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