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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VT8231 датащи(PDF) 112 Page - List of Unclassifed Manufacturers |
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VT8231 датащи(HTML) 112 Page - List of Unclassifed Manufacturers |
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112 / 132 page  VT8231 Preliminary Revision 0.8 October 29, 1999 -106- Hardware Monitor I/O Space Registers 7HFKQRORJLHV ,QF :H &RQQHFW :H &RQQHFW Offset 41 –Hardware Monitor Interrupt Status 1...........RO 7 Fan 2 Error 0 No error ..................................................default 1 Fan 2 count limit exceeded 6 Fan 1 Error 0 No error ..................................................default 1 Fan 1 count limit exceeded 5 Reserved ........................................ always reads 0 4 TSENS1 Temperature Error 0 No error ..................................................default 1 High or low hot temperature limit exceeded. The interrupt mode is determined by Temperature Resolution register Rx4B[1-0]. 3 VSENS3 Voltage Error (5V) 0 No error ..................................................default 1 High or low limit exceeded 2 Internal Core VCC Voltage Error (3.3V) 0 No error ..................................................default 1 High or low limit exceeded 1 VSENS2 Voltage Error (2.5V NB Core Voltage) 0 No error ..................................................default 1 High or low limit exceeded 0 VSENS1 Voltage Error (2.0V CPU Core Voltage) 0 No error ..................................................default 1 High or low limit exceeded Offset 42 –Hardware Monitor Interrupt Status 2...........RO 7 TSENS3 (Internal Bandgap) Temp Error 0 No error ..................................................default 1 High or low hot temperature limit exceeded. Interrupt mode is determined by Rx4B[5-4]. 6-5 Reserved ........................................ always reads 0 4 Chassis Error 0 No error ..................................................default 1 Chassis Intrusion has gone high 3 TSENS2 Temperature Error 0 No error ..................................................default 1 High or low hot temperature limit exceeded. Interrupt mode is determined by Rx4B[3-2]. 2-1 Reserved ........................................ always reads 0 0 VSENS4 Voltage Error (12V) 0 No error ..................................................default 1 High or low limit exceeded Note: When either status register is read, status conditions in that register are reset. In the case of voltage priority indications, if two or more voltages were out of limits, then another indication would automatically be generated if it was not handled during interrupt service. Errant voltages may be disabled in the control register until the operator has time to clear the errant condition or set the limit higher or lower. Offset 43 –Hardware Monitor Interrupt Mask 1 .......... RW 7 Fan 2 Count Error Mask 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 6 Fan 1 Count Error Mask 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 5 TSENS1 Thermal Alarm Control Mask 0 Enable TSENS1 over-temp condition to control the thermal alarm (function 4 Rx40[7] automatic CPU clock throttling must be set )def 1 Disable 4 TSENS1 Temperature Error Mask 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 3 VSENS3 Voltage Error Mask (5V) 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 2 Internal Core VCC Voltage Error Mask (3.3V) 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 1 VSENS2 Voltage Error Mask (2.5V NB Core) 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 0 VSENS1 Voltage Error Mask (2.0V CPU Core) 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set Offset 44 –Hardware Monitor Interrupt Mask 2 .......... RW 7 TSENS3 Temperature Error Mask 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 6 TSENS3 Thermal Alarm Control Mask 0 Enable TSENS3 over-temp condition to control the thermal alarm (function 4 Rx40[7] automatic CPU clock throttling must be set) def 1 Disable 5 TSENS2 Thermal Alarm Control Mask 0 Enable TSENS2 over-temp condition to control the thermal alarm (function 4 Rx40[7] automatic CPU clock throttling must be set) def 1 Disable 4 Chassis Error Mask 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 3 TSENS2 Temperature Error Mask 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set 2-1 Reserved ........................................ always reads 0 0 VSENS4 Voltage Error Mask (12V) 0 Enable interrupt on error status bit set ......... def 1 Disable interrupt on error status bit set |
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