VT8231 datasheet(110/132 Pages) ETC

110 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-104-

Hardware Monitor I/O Space Registers

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Hardware Monitor I/O Space Registers

The I/O base address for access to the Hardware Monitor

registers is defined in Rx71-70 of function 4 PCI configuration

space. The hardware monitor I/O space is enabled for I/O

access by the system if Rx74[0] = 1.

Offset 13 – Analog Data 15-8 ...........................................RW

Offset 14 – Analog Data 7-0 .............................................RW

Offset 15 – Digital Data 7-0 ..............................................RW

Offset 16 – Channel Counter............................................RW

Offset 17 – Data Valid & Channel Indicators.................RW

Offset 1D – TSENS3 Hot Temperature High Limit .......RW

Offset 1E – TSENS3 Hot Temp Hysteresis Lo Limit......RW

Offset 1F – TSENS3 Temperature Reading....................RW

Temperature sensor 3 is an internal bandgap-type sensor which

has 10-bit resolution. The high order 8 bits are stored here and

the low order 2 bits are stored in Rx49[7-6]. Only the high

order 8 bits are used for comparison with the limit values in

offsets 1D and 1E.

Offset 20 – TSENS1 Temperature Reading ....................RW

Temperature sensor 1 is an external sensor input on pin W13

which has 10-bit resolution. The high order 8 bits are stored

here and the low order 2 bits are stored in Rx4B[7-6]. Only

the high order 8 bits are used for comparison with the limit

values in offsets 39 and 3A.

Offset 21 – TSENS2 Temperature Reading ....................RW

Temperature sensor 2 is an external sensor input on pin Y13

which has 10-bit resolution. The high order 8 bits are stored

here and the low order 2 bits are stored in Rx49[5-4]. Only

the high order 8 bits are used for comparison with the limit

values in offsets 3D and 3E.

Offset 22 – VSENS1 (Pin U13) Voltage Reading (2.0V).RW

Offset 23 – VSENS2 (Pin V13) Voltage Reading (2.5V).RW

Offset 24 – Internal Core Voltage Reading (3.3V) .........RW

Offset 25 – VSENS3 (Pin W14) Voltage Reading (5V) ..RW

Offset 26 – VSENS4 (Pin Y14) Voltage Reading (12V)..RW

Offset 27 – Reserved (-12V Sense Voltage Reading) ......RW

Offset 28 – Reserved (-5V Sense Voltage Reading) ........RW

Offset 29 – FAN1 (Pin T12) Count Reading................... RW

Offset 2A – FAN2 (Pin U12) Count Reading.................. RW

The above two locations store the number of counts of the

internal clock per fan revolution.

Offset 2B – VSENS1 Voltage High Limit (CPU 2.0V)... RW

Offset 2C – VSENS1 Voltage Low Limit (CPU 2.0V) ... RW

Offset 2D – VSENS2 Voltage High Limit (NB 2.5V) ..... RW

Offset 2E – VSENS2 Voltage Low Limit (NB 2.5V) ...... RW

Offset 2F – Internal Core Voltage High Limit (3.3V).... RW

Offset 30 – Internal Core Voltage Low Limit (3.3V) ..... RW

Offset 31 – VSENS3 Voltage High Limit (5V)................ RW

Offset 32 – VSENS3 Voltage Low Limit (5V) ................ RW

Offset 33 – VSENS4 Voltage High Limit (12V).............. RW

Offset 34 – VSENS4 Voltage Low Limit (12V) .............. RW

Offset 35 – Reserved (-12V Sense High Limit) ............... RW

Offset 36 – Reserved (-12V Sense Low Limit)................ RW

Offset 37 – Reserved (-5V Sense High Limit) ................. RW

Offset 38 – Reserved (-5V Sense Low Limit).................. RW

Offset 39 – TSENS1 Hot Temperature High Limit........ RW

Offset 3A – TSENS1Hot Temp Hysteresis Lo Limit...... RW

Offset 3B – FAN1 Fan Count Limit ................................ RW

Offset 3C – FAN2 Fan Count Limit ................................ RW

The above two locations store the number of counts of the

internal clock per fan revolution for the low limit of the fan

speed.

Offset 3D – TSENS2 Hot Temperature High Limit....... RW

Offset 3E – TSENS2 Hot Temp Hysteresis Lo Limit ..... RW

Offset 3F – Stepping ID Number..................................... RW

Note:

For high limits, comparisons are “greater than”

comparisons. For low limits, comparisons are “less than or

equal” comparisons.

One consequence of the above is that if high limits are set to

all ones (FFh or 11111111b), interrupts are disabled for high

limits (i.e., interrupts will only be generated for cases when

voltages are equal to or below the low limits).

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