VT8231 datasheet(75/132 Pages) ETC

75 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-69-

Function 1 Registers - Enhanced IDE Controller

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Function 1 Registers - Enhanced IDE Controller

This Enhanced IDE controller interface is fully compatible

with the SFF 8038i v.1.0 specification. There are two sets of

software accessible registers -- PCI configuration registers and

Bus Master IDE I/O registers. The PCI configuration registers

are located in the function 1 PCI configuration space of the

VT8231. The Bus Master IDE I/O registers are defined in the

SFF8038i v1.0 specification.

PCI Configuration Space Header

Offset 1-0 - Vendor ID (1106h=VIA) ................................RO

Offset 3-2 - Device ID (0571h=IDE Controller) ...............RO

Offset 5-4 - Command.......................................................RW

15-10 Reserved

........................................ always reads 0

Fast Back to Back Cycles ....... default = 0 (disabled)

SERR# Enable......................... default = 0 (disabled)

Address Stepping ...................... fixed at 1 (enabled)

A value of 1 provides additional address decode time

to IDE devices.

Parity Error Response ............ default = 0 (disabled)

VGA Palette Snoop ....................fixed at 0 (disabled)

Memory Write & Invalidate .....fixed at 0 (disabled)

Special Cycles .............................fixed at 0 (disabled)

2Bus Master ............................. default = 0 (disabled)

S/G operation can be issued only when the “Bus

Master” bit is enabled.

Memory Space............................fixed at 0 (disabled)

I/O Space

............................. default = 0 (disabled)

When the “I/O Space” bit is disabled, the device will

not respond to any I/O addresses for both compatible

and native mode.

Offset 7-6 - Status ...............................................................RO

Detected Parity Error .................................fixed at 0

Signalled System Error...............................fixed at 0

Received Master Abort...............................fixed at 0

Received Target Abort ...............................fixed at 0

Signalled Target Abort ...............................fixed at 0

10-9 DEVSEL# Timing ..................default = 01 (medium)

Data Parity Detected...................................fixed at 0

Fast Back to Back .......................................fixed at 1

6-0

Reserved

........................................ always reads 0

Offset 8 - Revision ID (06) .................................................RO

0-7

Revision Code for IDE Controller Logic Block

Offset 9 - Programming Interface ................................... RW

Master IDE Capability........... fixed at 1 (Supported)

6-4

Reserved

........................................ always reads 0

Programmable Indicator - Secondary ...... fixed at 1

Supports both modes (may be set to either mode by

writing bit-2)

Reserved

........................................ always reads 0

Programmable Indicator - Primary .......... fixed at 1

Supports both modes (may be set to either mode by

writing bit-0)

Reserved

........................................ always reads 0

Compatibility Mode (fixed IRQs and I/O addresses):

Command Block

Control Block

Channel

Registers

IRQ

Pri

1F0-1F7

3F6

Sec

170-177

376

Native PCI Mode (registers are programmable in I/O space)

Command Block

Control Block

Channel

Registers

Pri

BA @offset 10h

BA @offset 14h

Sec

BA @offset 18h

BA @offset 1Ch

Command register blocks are 8 bytes of I/O space

Control registers are 4 bytes of I/O space (only byte 2 is used)

Offset A - Sub Class Code (01h=IDE Controller) ........... RO

Offset B - Base Class Code (01h=Mass Storage Ctrlr) ... RO

Offset C – Cache Line Size (00h)...................................... RO

Offset D - Latency Timer (Default=0)............................. RW

Offset E - Header Type (00h)............................................ RO

Offset F - BIST (00h) ......................................................... RO

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