VT8231 datasheet(32/132 Pages) ETC

32 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-26-

Pinouts

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Power Management and External State Monitoring

Signal Name

Pin #

I/O

Signal Description

PME# / GPI6

I / I

Power Management Event. (Rx74[1]=0) (1K PU to VCCS if not used)

EXTSMI# / GPI2

IOD / I

External System Management Interrupt. When enabled to allow it, a

falling edge on this input causes an SMI# to be generated to the CPU to

enter SMI mode. (10K PU to VCCS if not used) (3.3V only)

SMBALRT# / GPI7

I / I

SMB Alert (System Management Bus I/O space Rx08[3] = 1). When the

chip is enabled to allow it, assertion generates an IRQ or SMI or power

management event. (10K PU to VCCS if not used)

THRM / AOLGPI / GPI17

I / I / I

Monitor Input - Thermal Alarm. (Rx74[1]=1) (1K PU to VCCS if not

used)

LID / GPI4

I / I

Monitor Input - Notebook Computer Display Lid Open / Closed.

Used by the Power Management subsystem to monitor the opening and

closing of the display lid of notebook computers. Can be used to detect

either low-to-high and/or high-to-low transitions to generate an SMI#. The

VT8231 performs a 200 usec debounce of this input if Function 4 Rx40[5]

is set to 1. (10K PU to VCCS if not used)

RING# / GPI3

I / I

Monitor Input – Modem Ring. May be connected to external modem

circuitry to allow the system to be re-activated by a received phone call.

(10K PU to VCCS if not used)

BATLOW# / GPI5

I / I

Monitor Input - Battery Low. (10K PU to VCCS if not used)

CPUMISS / GPI16

I / I

Monitor Input - CPU Missing. Indicates whether the CPU is plugged in

correctly.

AOLGPI / GPI17 / THRM

I / I / I

Monitor Input - Awake On LAN External Event.

INTRUDER# / GPI8

I / I

Monitor Input – Chassis Intrusion.

RSMRST#

Resume Reset. Resets the internal logic connected to the VCCS power

plane and also resets portions of the internal RTC logic.

SUSA# / GPO1 / strap

O / O / I

Suspend Plane A Control (Rx74[7]=0 and Function 4 Rx54[2]=0).

Asserted during power management POS, STR, and STD suspend states.

Used to control the primary power plane. (10K PU to VCCS if not used)

SUSB# / GPO2

O / O

Suspend Plane B Control (Rx74[7]=0 and Function 4 Rx54[3]=0).

Asserted during power management STR and STD suspend states. Used

to control the secondary power plane. (10K PU to VCCS if not used)

SUSC# / GPO

O / O

Suspend Plane C Control.

Asserted during power management STD

suspend state. Used to control the tertiary power plane. Also connected to

ATX power-on circuitry.

SUSST1# / GPO3

O / O

Suspend Status 1 (Func4 Rx54[4] = 1 for GPO3). Typically connected to

the North Bridge to provide information on host clock status. Asserted

when the system may stop the host clock, such as Stop Clock or during

POS, STR, or STD suspend states. Connect 10K PU to VCCS.

SUSCLK / GPO4

O / O

Suspend Clock. 32.768 KHz output clock for use by the North Bridge

(e.g., Apollo MVP3 or MVP4) for DRAM refresh purposes.

Stopped

during Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VCCS.

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