VT8231 datasheet(70/132 Pages) ETC

70 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-64-

Function 0 Registers - PCI to ISA Bridge

7HFKQRORJLHV ,QF

:H &RQQHFW

Miscellaneous / General Purpose I/O

Offset 73-70 - Subsystem ID ............................................ WO

31-0 Subsystem ID / Vendor ID................. always reads 0

Contents may be read at offset 2C.

Offset 74 – GPIO Control 1..............................................RW

7APIC Enable

Disable (Pin U8 is GPIOD / MCCS#)....default

Enable (Pin U8 is SCIOUT#)

6SERIRQ Pin

SERIRQ input from DRQ2 (Pin H3)......default

SERIRQ input from DACK5# (Pin L4)

GPIOD Direction (Pin U8)

Input .....................................................default

Output (GPO11)

GPIOC Direction (Pin V14)

Input .....................................................default

1Output

GPIOB Direction (Pin U12)

Input .....................................................default

1Output

GPIOA Direction (Pin T14)

Input .....................................................default

1Output

THRM Enable (Pin T11)

PME# / GPI5 (see Func 4 Rx48[5]) .......default

1THRM

GPI0 / IOCHCK# Select

GPI0 .....................................................default

IOCHCK#

Offset 75 – GPIO Control 2 ............................................. RW

GPO7 Enable (Pin T7)

Pin defined as SLP#............................... default

Pin defined as GPO7

Reserved

........................................ always reads 0

GPO5 Enable (Pin V12)

Pin defined as PCISTP# ........................ default

Pin defined as GPO5

GPO4 Enable (Pin Y12)

Pin defined as CPUSTP# ....................... default

Pin defined as GPO4

FDC External IRQ / DRQ Via DACK2# / DRQ2

Pin G5 is FDCIRQ, pin H3 is FDCDRQ ..... def

Pin G5 is DACK2# or other alternate function

Pin H3 is DRQ2 or other alternate function

GPO25 Enable (Pin G5)

Rx75[3]=0: Pin G5 defined as DACK2# .... def

Pin G5 defined as GPO25

GPO24 Enable (Pin H3)

Rx75[3]=0: ............................................ default

Rx68[3]=0: Pin H3 defined as DRQ2

Rx68[3]=1: Pin H3 defined as SERIRQ

Pin H3 defined as GPO24

Positive Decode

Subtractive Decode................................ default

Positive Decode

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