VT8231 datasheet(69/132 Pages) ETC

69 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-63-

Function 0 Registers - PCI to ISA Bridge

7HFKQRORJLHV ,QF

:H &RQQHFW

Distributed DMA / Serial IRQ Control

Offset 61-60 - Distributed DMA Ch 0 Base / Enable......RW

15-4 Channel 0 Base Address Bits 15-4 .......... default = 0

Channel 0 Enable

Disable ...................................................default

1Enable

2-0

Reserved

........................................ always reads 0

Offset 63-62 - Distributed DMA Ch 1 Base / Enable......RW

15-4 Channel 1 Base Address Bits 15-4 .......... default = 0

Channel 1 Enable

Disable ...................................................default

1Enable

2-0

Reserved

........................................ always reads 0

Offset 65-64 - Distributed DMA Ch 2 Base / Enable......RW

15-4 Channel 2 Base Address Bits 15-4 .......... default = 0

Channel 2 Enable

Disable ...................................................default

1Enable

2-0

Reserved

........................................ always reads 0

Offset 67-66 - Distributed DMA Ch 3 Base / Enable......RW

15-4 Channel 3 Base Address Bits 15-4 .......... default = 0

Channel 3 Enable

Disable ...................................................default

1Enable

2-0

Reserved

........................................ always reads 0

Offset 69-68 – Serial IRQ Control ...................................RW

15-4 Reserved

........................................ always reads 0

ISA IRQ Asserted Via Serial IRQ (Pin H3 or L4)

Disable ...................................................default

1Enable

Serial IRQ Mode

Continuous Mode ...................................default

Quiet Mode

1-0

Serial IRQ Start-Frame Width

00 4 PCI Clocks ..........................................default

01 6 PCI Clocks

10 8 PCI Clocks

11 10 PCI Clocks

The frame size is fixed at 21 PCI clocks.

Offset 6B-6A - Distributed DMA Ch 5 Base / Enable.... RW

15-4 Channel 5 Base Address Bits 15-4........... default = 0

Channel 5 Enable

Disable................................................... default

1Enable

2-0

Reserved

........................................ always reads 0

Offset 6D-6C - Distributed DMA Ch 6 Base / Enable ... RW

15-4 Channel 6 Base Address Bits 15-4........... default = 0

Channel 6 Enable

Disable................................................... default

1Enable

2-0

Reserved

........................................ always reads 0

Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW

15-4 Channel 7 Base Address Bits 15-4........... default = 0

Channel 7 Enable

Disable................................................... default

1Enable

2-0

Reserved

........................................ always reads 0

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