VT8231 datasheet(65/132 Pages) ETC

65 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-59-

Function 0 Registers - PCI to ISA Bridge

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 46 - Miscellaneous Control 1.................................RW

PCI Master Write Wait States

0 Wait States ..........................................default

1 Wait State

6Gate INTR

Disable ...................................................default

1Enable

Flush Line Buffer for Int or DMA IOR Cycle

Disable ...................................................default

1Enable

Config Command Reg Rx04 Access (Test Only)

Normal: Bits 0-1=RO, Bit 3=RW..........default

Test Mode: Bits 0-1=RW, Bit-3=RO

Reserved (do not program)........................ default = 0

Reserved (no function) .............................. default = 0

PCI Burst Read Interruptability

Allow burst reads to be interrupted by ISA

master or DMA.......................................default

1Don’t allow PCI burst reads to be interrupted

Posted Memory Write Enable

Disable ...................................................default

1Enable

The Posted Memory Write function is automatically

enabled when Delay Transaction (see Rx47 bit-6) is

enabled, independent of the state of this bit.

Offset 47 - Miscellaneous Control 2 ................................ RW

CPU Reset Source

Use CPURST as CPU Reset .................. default

Use INIT as CPU Reset

PCI Delay Transaction Enable

Disable................................................... default

1Enable

The

"Posted

Memory

Write"

function

automatically enabled when this bit is enabled,

independent of the state of Rx46 bit-0.

EISA 4D0/4D1 Port Enable

Disable (ignore ports 4D0-1) ................. default

Enable (ports 4D0-1 per EISA specification)

Interrupt Controller Shadow Register Enable

Disable................................................... default

Enable (for test purposes, enable readback of

interrupt controller internal functions on I/O

reads from ports 20-21, A0-A1, A8-A9, and

C8-C9)

(Contact

VIA

Test

Engineering

department)

Reserved (always program to 0).............. default = 0

Note: Always mask this bit. This bit may read back

as either 0 or 1 but must always be

programmed with 0.

Write Delay Transaction Time-Out Timer

Disable................................................... default

1Enable

Read Delay Transaction Time-Out Timer

Disable................................................... default

1Enable

Software PCI Reset ...... write 1 to generate PCI reset

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