VT8231 datasheet(83/132 Pages) ETC

83 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-77-

Function 2 Registers - USB Controller Ports 0-1

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Function 2 Registers - USB Controller Ports 0-1

This Universal Serial Bus host controller interface is fully

compatible with UHCI specification v1.1. There are two sets

of software accessible registers: PCI configuration registers

and USB I/O registers. The PCI configuration registers are

located in the function 2 PCI configuration space of the

VT8231. The USB I/O registers are defined in UHCI

specification v1.1. The registers in this function control USB

ports 0-1 (see function 3 for ports 2-3).

PCI Configuration Space Header

Offset 1-0 - Vendor ID .......................................................RO

0-7

Vendor ID

................. (1106h = VIA Technologies)

Offset 3-2 - Device ID.........................................................RO

0-7

Device ID

(3038h = VT8231 USB Controller)

Offset 5-4 - Command.......................................................RW

15-8 Reserved

........................................ always reads 0

Address Stepping ...................... default=0 (disabled)

Reserved (parity error response) ..................fixed at 0

Reserved (VGA palette snoop) ....................fixed at 0

Memory Write and Invalidate . default=0 (disabled)

Reserved (special cycle monitoring) ............fixed at 0

2Bus Master ............................... default=0 (disabled)

Memory Space........................... default=0 (disabled)

I/O Space

............................... default=0 (disabled)

Offset 7-6 - Status ...........................................................RWC

Reserved (detected parity error).......... always reads 0

Signalled System Error.............................. default=0

Received Master Abort.............................. default=0

Received Target Abort .............................. default=0

Signalled Target Abort .............................. default=0

10-9 DEVSEL# Timing

00 Fast

01 Medium ......................................default (fixed)

10 Slow

11 Reserved

8-0

Reserved

........................................ always reads 0

Offset 8 - Revision ID (nnh) .............................................. RO

7-0

Silicon Revision Code (0 indicates first silicon)

06h Corresponds to Chip Revision D

Offset 9 - Programming Interface (00h) .......................... RO

Offset A - Sub Class Code (03h=USB Controller) .......... RO

Offset B - Base Class Code (0Ch=Serial Bus Controller)RO

Offset C – Cache Line Size (00h)...................................... RO

Offset D - Latency Timer ................................................. RW

7-0

Timer Value .......................................... default = 16h

Offset E - Header Type (00h)............................................ RO

Offset F - BIST (00h) ......................................................... RO

Offset 23-20 - USB I/O Register Base Address............... RW

31-16 Reserved

........................................ always reads 0

15-5 USB I/O Register Base Address. Port Address for

the base of the 32-byte USB I/O Register block,

corresponding to AD[15:5]

4-0

00001b

Offset 3C - Interrupt Line (00h)...................................... RW

7-4

Reserved

........................................ always reads 0

3-0

USB Interrupt Routing ........................ default = 16h

0000 Disabled ................................................. default

0001 IRQ1

0010 Reserved

0011 IRQ3

0100 IRQ4

0101 IRQ5

0110 IRQ6

0111 IRQ7

1000 IRQ8

1001 IRQ9

1010 IRQ10

1011 IRQ11

1100 IRQ12

1101 IRQ13

1110 IRQ14

1111 Disabled

Offset 3D - Interrupt Pin (04h)......................................... RO

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