VT8231 datasheet(80/132 Pages) ETC

80 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-74-

Function 1 Registers - Enhanced IDE Controller

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 54 – UltraDMA FIFO Control..............................RW

7-5

Reserved

........................................ always reads 0

One Frame For Each PCI Request For IDE PCI

Master Cycles

Disabled ................................................default

1Enabled

Grant ISA While Sharing Bus with SA & IDE in

IDLE State

Enable.....................................................default

Disable

Change Drive to Clear All FIFO & Internal States

Disabled

Enabled...................................................default

Add Dummy FIFO Push After End of Transfer

0Enabled

Disabled .................................................default

This bit is normally set to 0 for effective handling of

transfer lengths that are not doubleword multiples

Complete DMA Cycle with Transfer Size Less

Than FIFO Size

Enabled...................................................default

Disabled

Offset 61-60 - Primary Sector Size .................................. RW

15-12 Reserved

........................................ always reads 0

11-0 Number of Bytes Per Sector ... def=200h (512 bytes)

Offset 69-68 - Secondary Sector Size .............................. RW

15-12 Reserved

........................................ always reads 0

11-0 Number of Bytes Per Sector ... def=200h (512 bytes)

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