VT8231 datasheet(18/132 Pages) ETC

18 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-12-

Pinouts

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Advanced Programmable Interrupt Controller (APIC) Interface

Signal Name

Pin #

I/O

Signal Description

WSC# / APICREQ# / GPI14

I / I / I

Internal APIC Write Snoop Complete. Asserted by the north

bridge to indicate that all snoop activity on the CPU bus initiated

by the last PCI-to-DRAM write is complete and that it is safe to

perform an APIC interrupt.

External APIC Request. Asserted by external APIC synchronous

to PCICLK prior to sending an interrupt over the APIC serial bus.

This signals the VT8231 to flush its internal buffers.

APICD0 / APICCS# / GPIO28

O / O / IO

Internal APIC Data 0.

External APIC Chip Select. The VT8231 drives this signal active

to select an external APIC (if used). This occurs if the external

APIC is enabled and a PCI cycle is detected within the

programmed APIC address range.

APICD1 / APICACK# / GPIO29

O / O / IO

Internal APIC Data 1.

External APIC Acknowledge. Asserted by the VT8231 to indicate

that it internal buffers have been flushed (in response to

APICREQ#). This indicates to the external APIC that the

VT8231’s internal buffers have been flushed and that it is OK for

the APIC to send its interrupt.

APICCLK / GPI9

I / I

APIC Clock.

SCIOUT# / GPIOD

/ GPIO30 / DTEST

O / IO

IO / O

SCI Out.

Used to route internally generated SCI and SMBus

interrupts to external APIC (if used).

Defined as SCIOUT# if

external APIC enabled (function 0 Rx74[7] = 1).

AIRQ / MCOL

G17