VT8231 datasheet(111/132 Pages) ETC

111 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-105-

Hardware Monitor I/O Space Registers

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 40 –Hardware Monitor Configuration ................RW

Initialization

Normal operation ...................................default

Restore

power-up

default

values

this

the FAN/RST#/OS# register, and the OS#

Configuration

Temperature

Resolution

This bit automatically clears itself

since the power-on default is 0.

Chassis Intrusion Reset

Normal operation ...................................default

Reset the Chassis Intrusion pin

5-4

Reserved (R/W) ........................................ default = 0

Hardware Monitor Interrupt Clear

Normal operation

Clear the hardware monitor interrupt output

(does not effect the contents of the interrupt

status register). Normally set during interrupt

service ....................................................default

Reserved

........................................ always reads 0

Hardware Monitor Interrupt Enable

Disable hardware monitor interrupt output.. def

Enable hardware monitor interrupt output

0Start

Place hardware monitor in standby mode.... def

Enable startup of hardware monitor logic.

At startup, limit checking functions and

scanning begins.

All high and low limits

should be set prior to turning on this bit. Note:

the hardware monitor interrupt output will not

be cleared if the user writes a zero to this bit

after an interrupt has occurred (the hardware

monitor interrupt clear bit must be used for this

purpose).

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