VT8231 datasheet(17/132 Pages) ETC

17 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-11-

Pinouts

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CPU Interface

Signal Name

Pin #

I/O

Signal Description

CPURST

CPU Reset. The VT8231 asserts CPURST to reset the CPU during

power-up.

INTR

CPU Interrupt. INTR is driven by the VT8231 to signal the CPU that

an interrupt request is pending and needs service.

NMI

Non-Maskable Interrupt.

NMI is used to force a non-maskable

interrupt to the CPU.

The VT8231 generates an NMI when either

SERR# or IOCHK# is asserted.

INIT

Initialization.

The VT8231 asserts INIT if it detects a shut-down

special cycle on the PCI bus or if a soft reset is initiated by the register

STPCLK#

Stop Clock.

STPCLK# is asserted by the VT8231 to the CPU to

throttle the processor clock.

SMI#

System Management Interrupt. SMI# is asserted by the VT8231 to

the CPU in response to different Power-Management events.

FERR#

Numerical Coprocessor Error. This signal is tied to the coprocessor

error signal on the CPU. Internally generates interrupt 13 if active.

IGNNE#

Ignore Numeric Error. This pin is connected to the “ignore error” pin

on the CPU.

SLP# / GPO7

Sleep (Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1

CPUs only. Not currently used with socket-7 CPUs.

A20M#

A20 Mask. Connect to A20 mask input of the CPU to control address

bit-20 generation. Logical combination of the A20GATE input (from

internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

DTD+

Analog I

CPU DTD (Thermal Diode) Channel Plus. Connect to cathode of first

external temperature sensing diode.

DTD-

Analog I

CPU DTD (Thermal Diode) Channel Minus. Connect to anode of

first external temperature sensing diode.

Note: Connect each of the above signals to 4.7K

Ω pullup resistors to VCC3.

Strap Options

Signal Name

Pin #

I/O

Signal Description

Strap / SUSA#

I / O

CPURST / INIT Polarity

Strap / MCCS#

I / O

CPU Frequency Strapping

H: Disable

L: Enable

Strap / PCS0#

I / O

SD Bus Width

H: 16-Bit

L: 8-Bit

Strap / SA16

Y14

I / IO

BIO ROM Interface

H: LPC

L: Conventional

Strap / SA17

T13

I / IO

Auto Reboot

H: Disable

L: Enable

Strap / KBCS# / ROMCS#

I / O / O

CPU Type

4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1

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