VT8231 datasheet(92/132 Pages) ETC

92 / 132 page

VT8231

Preliminary Revision 0.8 October 29, 1999

-86-

Function 4 Regs - Power Management, SMBus and HWM

7HFKQRORJLHV ,QF

:H &RQQHFW

Offset 4B-48 – Power Management I/O Base .................RW

31-16 Reserved

........................................ always reads 0

15-7 Power Management I/O Register Base Address.

Port Address for the base of the 128-byte Power

Management I/O Register block, corresponding to

AD[15:7].

The "I/O Space" bit at offset 41 bit-7

enables access to this register block. The definitions

of the registers in the Power Management I/O

following

the

Power-Management-Specific

PCI

Configuration register descriptions and the Power

Management Subsystem overview.

6-0

0000001b

Offset 4C – Host Bus Power Management Control........RW

7-4

Thermal Duty Cycle (THM_DTY)

This 4-bit field determines the duty cycle of the

STPCLK# signal when the THRM# pin is asserted

low. The field is decoded as follows:

0000 Reserved.................................................default

0001 0-6.25%

0010 6.25-12.50%

0011 18.75-25.00%

0100 31.25-37.50%

0101 37.50-43.75%

0110 43.75-50.00%

0111 50.00-56.25%

1000 56.25-62.50%

1001 62.50-68.75%

1010 68.75-75.00%

1011 75.00-87.50%

1100 75.00-81.25%

1101 81.25-87.50%

1110 87.50-93.75%

1111 93.75-100%

3THRM Enable

Disable ...................................................default

1Enable

Frame Input as Resume Event in C3

Disable ...................................................default

1Enable

Reserved

........................................ always reads 0

CPU Stop Grant Cycle Select

From Halt and Stop Grant Cycle ............default

From Stop Grant Cycle

This bit is combined with I/O space Rx2C[3] for

controlling the start of CPUSTP# assertion during

system suspend mode:

Rx2C[3]

Rx4C[0]

Function 4

I/O Space

Cfg Space

CPUSTP# Assertion

Immediate

Wait for CPU Halt

/ Stop Grant cycle

Wait for CPU

Stop Grant cycle

Offset 4D – Throttle / Clock Stop Control...................... RW

Throttle Timer Reset ......................................def = 0

6-5

Throttle Timer

0x 4-Bit .................................................... default

10 3-Bit

11 2-Bit

Fast Clock (7.5us) as Throttle Timer Tick

Disable................................................... default

1Enable

Reserved

........................................ always reads 0

Internal Clock Stop for PCI Idle

Disable................................................... default

1Enable

Internal Clock Stop During C3

Disable................................................... default

1Enable

Internal Clock Stop During Suspend

Disable................................................... default

1Enable

VT8231 датащи(PDF) 92 Page - List of Unclassifed Manufacturers

VT8231 датащи(HTML) 92 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL