PC87413 datasheet(135/257 Pages) NSC

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7.0

General-Purpose Input/Output (GPIO) Ports

This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.

For device specific implementation, see Section 3.14 on page 70.

7.1

OVERVIEW

The GPIO port is an 8-bit port, connected to eight pins. It features:

• Software capability to control and read pin levels.

• Flexible system notification by several means, based on the pin level or level transition.

• Ability to capture and route events and their associated status.

• Back-drive protected pins.

GPIO port operation is associated with two sets of registers:

• Pin Configuration registers mapped in the Device Configuration space. These registers are used to set up the logical

behavior of each pin. There are three registers for each GPIO pin: GPIO Pin Configuration registers 1 and 2 (GPCFG1,

GPCFG2) and the GPIO Pin Event Routing register (GPEVR).

• Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and GPIO

Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by the base

address registers in the GPIO Device Configuration). They are used to control and/or read the pin values and to handle

system notification. Each runtime register corresponds to the 8-pin port, such that bit ‘n’ in each one of the four registers

is associated with GPIOXn pin, where ‘X’ is the port number.

Each GPIO pin is associated with configuration bits and the corresponding bit slice of the four runtime registers, as shown

in Figure 35.

The functionality of the GPIO port is divided into basic functionality, which includes the control and reading of the GPIO pins

and enhanced functionality, which includes wake-up event detection and system notification. Basic functionality is described

in Section 7.2; enhanced functionality is described in Section 7.3.

Figure 35. GPIO Port Architecture

GPIO Pin

Select (GPSEL)

Conﬁguration 1 and 2

GPDOX

GPDIX

GPEVENX

GPEVSTX

Runtime

Registers

GPIOX Base Address

Event

Bit n

Port and Pin

8 GPCFG

Registers

GPIOXn

GPIOXn CNFG

Interrupt Request

GPIOXn

Port Logic

X = port number

n = pin number (0 to 7)

Pending

Indication

SIOSMI

GPIO Pin Event

Routing (GPEVR)

8 GPEVR

Registers

GPIOXn ROUTE

Select

Event

Routing

Control

Registers

(GPCFG1 and GPCFG2)

SWC

SIOSCI

Power Button

Pulse Enable

ONCTL

GPIO

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