PC87413 datasheet(139/257 Pages) NSC

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7.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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System notification through IRQ, SMI or SCI (see Section 9.2.1 on page 162) can be initiated by software by writing to the

Data Out bit (in the GPDO register) of a GPIO pin. This is possible only if the output of the corresponding GPIO pin is en-

abled, pin multiplexing is selected for the GPIO function (see Section 1.3 on page 20) and the GPIO event is routed to IRQ,

SMI or SCI. System notification is asserted according to the actual level at the GPIO pin driven by the GPIO output and/or

by external circuitry. The level driven by the GPIO output should not cause a contention with the level driven by the external

circuitry.

A pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not

be released by software (except for disabling the source) as long as the pin is at active level. When level event is used, it is

also recommended to disable the input debouncer.

Upon deactivation of the GPIO functional block and while the VDD power is Off, access through the LPC bus to the runtime

registers (GPEVST and GPEVEN) is disabled. All means of system notification that include the target IRQ number are de-

tached from the GPIO and de-asserted.

When the VDD power is Off, the status bits of the GPIO pins connected to a VDD-powered device (VDDLOAD = 1) are cleared,

however the status bits of the GPIO pins connected to a VSB-powered device (VDDLOAD = 0) is not affected.

Before enabling any system notification, it is recommended to set the desired event configuration and then verify that the

status registers are cleared.

7.4

GPIO PORT REGISTERS

The following abbreviations are used to indicate the Register Type:

R/W

= Read/Write.

= Read from a speciﬁc register (write to the same address is to a different register).

= Write (see above).

= Read Only.

= Write Only. Reading from the bit returns 0.

R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.

7.4.1

GPIO Pin Configuration Registers Structure

For each Port, there is a group of eight identical sets of configuration registers. Each set is associated with one GPIO pin.

The entire group is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register (see

Section 3.14.3 on page 72), which functions as an index register, and the specific GPCFG1, GPEVR and GPCFG2 registers

that reflect the configuration of the currently selected pin (see Table 34). All these registers are VSB powered.

Table 34. GPIO Conﬁguration Registers

Index

Conﬁguration Register or Action

Type

Power Well

Reset

F0h

GPIO Pin Select register (GPSEL).

R/W

VSB

00h

F1h

GPIO Pin Conﬁguration register 1 (GPCFG1).

R/W

VSB

Note1

1. See Section 3.14.3 on page 72.

F2h

GPIO Pin Event Routing register (GPEVR).

R/W

VSB

01h

F3h

GPIO Pin Conﬁguration register 2 (GPCFG2).

R/W

VSB

00h

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