PC87413 datasheet(138/257 Pages) NSC

138 / 257 page

7.0 General-Purpose Input/Output (GPIO) Ports (Continued)

www.national.com

138

Revision1.2

Event Debounce Enable

The input signal can be debounced for about 15 msec before entering the detector. To ensure that the signal is stable, the

signal state is transferred to the event detector only after a debouncing period during which the signal has no transitions.

The debouncer adds a 16 msec delay to both assertion and de-assertion of the event pending indicator (IRQ, SMI, SCI).

The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG1 register).

Event Type and Polarity

Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin tran-

sition either from high to low or low to high. A level event may be detected when the source pin is either at high or low level.

The trigger type is determined by Event Type (bit 4 of the GPCFG1 register). The direction of the transition (for edge) or the

polarity of the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG1 register).

The term active edge refers to a change in a GPIO pin level that matches the Event Polarity bit (1 for rising edge and 0 for

falling edge). Active level refers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level).

The corresponding bit of the GPEVST register is set by hardware whenever an active edge or an active level is detected

regardless of the GPEVEN register setting. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.

A GPIO pin is in event pending state if an active event occurred (the corresponding bit of the GPEVST register is set) and

the corresponding bit of the GPEVEN register is set.

7.3.2

System Notification

System notification on GPIO-triggered events is achieved by asserting at least one of the following output pins:

• Interrupt Request (via the Interrupt Serializer in the LPC Bus Interface).

• System Management Interrupt (SIOSMI, via the System Wake-Up Control).

The system notification for each GPIO pin is controlled by the corresponding bit in the GPEVEN register and the bits of the

GPEVR register. System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1.

The bits of the GPEVR register select the means of system notification (IRQ or SMI) that the detected GPIO event is routed

to. The event routing mechanism is described in Figure 38.

Figure 38. GPIO Event Routing Mechanism for System Notiﬁcation

The system notification to the target is asserted if at least one GPIO pin is in event pending state.

The selection of the target (the means of system notification) is determined by the GPEVR register. If IRQ is selected as one

of the means for the system notification, the specific IRQ number is determined by the IRQ selection procedure of the device

configuration. The assertion of IRQ (as a means of system notification) is disabled either when the GPIO functional block is

deactivated or when the VDD power is Off.

The assertion of SMI is independent of the activation of the GPIO functional block. SMI from GPIO pins connected to a device

pins connected to a device powered by VSB (VDDLOAD = 0) is not affected by the status of the VDD power.

GPIO Event Pending Indication

SIOSMI

IRQ

Event

Routing

Logic

Enable

IRQ

Event Routing Register

Bit 1

Bit 0

(GPEVR)

Routed Events

from other GPIO Pins

Routing

Enable

SMI

GPIO Pin

GPIO Event to

PC87413 датащи(PDF) 138 Page - National Semiconductor (TI)

PC87413 датащи(HTML) 138 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL