PC87413 datasheet(131/257 Pages) NSC

131 / 257 page

6.0 ACCESS.bus Interface (Continued)

Revision 1.2

131

www.national.com

6.3.6

ACCESS.bus TRI-STATE Register (ACBTRIS)

This register provides a fast way to float the outputs of one or more modules through the ACCESS.bus without having to

access their TRI-STATE Control bit in the Special Configuration register at index F0h. The module outputs enter TRI-STATE

only when the module is disabled (see Section 6.3.5 on page 130). The register is reset by hardware to 00h.

Power Well: VSB

Location:

Offset 04h

Type:

R/W

Bit

43210

Name

Reserved

KBMSTRIS

SER1TRIS

SER2TRIS

PARPTRIS

FDCTRIS

Reset

00000

Bit

Description

7-5

Reserved.

KBMSTRIS (Keyboard and Mouse Outputs TRI-STATE). When set to 1 and the module is disabled, this bit

forces the outputs of the Keyboard and Mouse Controller to be in TRI-STATE regardless of bit 0 in the Keyboard

Conﬁguration register (see Section 3.13.3 on page 69).

0: Enabled or Disabled, according to bit 0 in the Keyboard Configuration register (default)

1: Outputs in TRI-STATE

SER1TRIS (Serial Port 1 Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the

outputs of the Serial Port 1 module to be in TRI-STATE regardless of bits 6 and 0 in the Serial Port 1

Conﬁguration register (see Section 3.11.3 on page 66).

0: Enabled or Disabled, according to bits 6 and 0 in the Serial Port 1 Configuration register (default)

1: Outputs in TRI-STATE

SER2TRIS (Serial Port 2 Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the

outputs of the Serial Port 2 module to be in TRI-STATE regardless of bits 6 and 0 in the Serial Port 2

Conﬁguration register (see Section 3.10.3 on page 64).

0: Enabled or Disabled, according to bits 6 and 0 in the Serial Port 2 Configuration register (default)

1: Outputs in TRI-STATE

PARPTRIS (Parallel Port Outputs TRI-STATE). When set to 1 and the module is disabled, this bit forces the

outputs of the Parallel Port module to be in TRI-STATE regardless of bit 0 in the Parallel Port Conﬁguration

0: Enabled or Disabled, according to bit 0 in the Parallel Port Configuration register (default)

1: Outputs in TRI-STATE

FDCTRIS (Floppy Disk Controller Outputs TRI-STATE). When set to 1 and the module is disabled, this bit

forces the outputs of the Floppy Disk Controller module to be in TRI-STATE regardless of bit 0 in the FDC

Conﬁguration register (see Section 3.8.3 on page 59).

0: Enabled or Disabled, according to bit 0 in the FDC Configuration register (default)

1: Outputs in TRI-STATE

PC87413 датащи(PDF) 131 Page - National Semiconductor (TI)

PC87413 датащи(HTML) 131 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL