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PC87413 датащи(PDF) 136 Page - National Semiconductor (TI) |
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PC87413 датащи(HTML) 136 Page - National Semiconductor (TI) |
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136 / 257 page ![]() 7.0 General-Purpose Input/Output (GPIO) Ports (Continued) www.national.com 136 Revision1.2 7.2 BASIC FUNCTIONALITY The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and GPDI. The configuration and operation of a single pin GPIOXn (pin ‘n’ in port ‘X’) is shown in Figure 36. Figure 36. GPIO Basic Functionality 7.2.1 Configuration Options The GPCFG1 register controls the following basic configuration options: • Port Direction - Controlled by the Output Enable bit (bit 0). • Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the upper tran- sistor of the output buffer. • Static Pull-Up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2). • Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output configuration. The lock is controlled by bit 3. It disables writes to the GPDO register bits, to bits 0-3 of the GPCFG1 register (including the Lock bit itself) and to bits 4-6 of the GPCFG2 register. Once locked, it can be released by reset or by the UNLOCKG bit in the ACBLKCTL register (see Section 6.3.4 on page 128 - PC87413 and PC87417). The GPCFG2 register controls the following basic configuration options: • Load Protection - Disables the Output Buffer (if enabled), the Static Pull-Up (if enabled) and the Input Buffer (if the Port is not a GPO type) if the specific GPIO pin is connected to a VDD-powered device and the VDD power is not present (No_Vdd). This function is controlled by the VDD-powered Load bit (bit 4). Pin Data Out Data In Output Enable Output Lock Type Static Pull-Up Pull-Up Enable Push-Pull =1 Pull-Up Control Read Only Read/Write (Bit 3) (Bit 2) (Bit 1) (Bit 0) Lock Lock Lock GPIO Pin Configuration Registers 1 and 2 (GPCFG1) ACCESS.bus LPC Bus VDD-powered Load Bus Control (Bits 6,5) (Bit 4) Lock Lock No_Vdd (GPCFG2) Pin (GPDI) (GPDO) |
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