PC87413 datasheet(127/257 Pages) NSC

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6.0 ACCESS.bus Interface (Continued)

Revision 1.2

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6.3.2

ACCESS.bus Control/Status Register (ACBCST)

This register controls the ACCESS.bus interface and holds the status of the last transactions. On reset, it is cleared (01h).

Power Well:VSB

Location:

Offset 00h

Type:

Varies per bit

Bit

76543210

Name

OFFLDN

ILGCOM

PECERR

BUSERR

LOWCKTO

ACCLVIOL

VDDSTAT

PECAVAIL

Reset

00000001

Bit

Type

Description

R/W1C OFFLDN (Accessed LDN Powered-off Flag). Indicates that the Logical Device accessed through the

command byte (only for Internal Access mode, i.e., when INEX = 0) is powered-off (relevant for the

Legacy functional blocks powered from the VDD plane). Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Powered Logical Device accessed (default)

1: Unpowered Logical Device accessed

R/W1C ILGCOM (Illegal Command Flag). Indicates that an illegal command code or an incorrect number of

address/data bytes was received or requested for transmission (by last byte NACK or Stop control).

Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Correct protocol (default)

1: Illegal command or number of bytes

R/W1C PECERR (PEC Error Flag). Indicates that a PEC error was detected in the write transaction bytes that

were received from the master. This bit is not updated if the master does not send a PEC byte. Writing

‘1’ clears this bit; writing ‘0’ is ignored.

0: Correct PEC (default)

1: CRC of the received bytes differs from the received PEC

R/W1C BUSERR (Bus Error Flag). Indicates that an unexpected Start, Restart or Stop Condition was detected

during a read or write transaction. Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Correct transaction (default)

1: Illegal Start, Restart or Stop Condition

R/W1C LOWCKTO (Low Clock Timeout Flag). Indicates that the ACBCLK signal was detected low for longer

than the maximum allowed “cumulative clock low extend time” during a transaction, as deﬁned in

Section 11.5.6 on page 246. Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Correct clock low timing (default)

1: Clock low timeout

R/W1C ACCLVIOL (Access Lock Violation Flag). Indicates that an LPC access to a functional module locked

for sole use by ACCESS.bus was detected. Writing ‘1’ clears this bit; writing ‘0’ is ignored.

0: Correct LPC access (default)

1: LPC access to a locked functional module

1RO

VDDSTAT (VDD Power Status). Indicates the actual status of the VDD power supply to the PC8741x

device.

0: VDD power Off

1: VDD power On

0RO

PECAVAIL (PEC Feature Available). Enables the master to detect the availability of the PEC

implementation in the slave.

0: Peripheral does not support PEC

1: Peripheral supports PEC (default and fixed value for PC8741x devices)

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