PC87413 datasheet(125/257 Pages) NSC

125 / 257 page

6.0 ACCESS.bus Interface (Continued)

Revision 1.2

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Write External Transaction (PC87417)

This transaction writes a byte of data to a memory device or to an I/O port connected to the X-Bus. The chip-select for the

device is selected by the XBCSN field in the command byte. The specific memory location or I/O port register is accessed

using a 27-bit offset address (from the base of the chip-select). The 27-bit offset address is broken into four bytes: XA26-

XA24 in the Command byte and XA23-XA16, XA15-XA8 and XA7-XA0 in three successive Offset Address bytes. If PEC is

supported, the master sends a PEC byte at the end of the transaction.

Read External Transaction (PC87417)

This transaction reads a byte of data from a memory device or from an I/O port connected to the X-Bus. The chip-select for

the device is selected by the XBCSN field in the command byte. The specific memory location or I/O port register is accessed

using a 27-bit offset address (from the base of the chip-select). The 27-bit offset address is broken in four bytes: XA26-XA24

in the Command byte and XA23-XA16, XA15-XA8 and XA7-XA0 in three successive Offset Address bytes. This transaction

is executed in two phases:

The master executes an ACCESS.bus write transaction, which conveys the Command (Read), chip-select and Offset

Address information to the PC8741x device. During this phase, the data is read from the speciﬁc memory location or

I/O port register into the Read Buffer. This phase has no Stop Condition.

Following a Restart condition, the master executes an ACCESS.bus read transaction. During this phase the data is

transferred from the Read Buffer to the master. At the end of this phase, the PC8741x device returns a PEC byte if

required by the master. The calculated PEC value is based on the bytes transferred during both phases.

6.2.10

Transaction Execution

The ACCESS.bus uses the internal bus of the PC8741x device to access the internal modules (except its own registers) or

to bridge transactions to the X-Bus (see “Block Diagram” on page 1). Since the same internal bus is also used independently

by the LPC bus, the duration of the ACCESS.bus use of the internal bus is held to a minimum.

At the highest ACBCLK frequency (100 KHz), the longest ACCESS.bus transaction (Read External) takes at least 750

µs

to complete. In order not to stall the internal bus for such a long time, the ACCESS.bus transactions are executed as follows:

Write - data is written through the internal bus at the end of the transaction after the Stop condition is detected; the

next ACCESS.bus transaction can start immediately while the present data is written through the internal bus.

Read - data is read through the internal bus during the second part of the transaction (beginning with Restart), after

the Slave Address is received and before it is acknowledged (ACK); while the data is read through the internal bus,

the ACBCLK signal is held low, indicating to the ACCESS.bus master that PC8741x device is not ready (see Section

6.2.7 on page 120).

The duration of the ACCESS.bus transaction through the internal bus is longer for external access (X-Bus devices -

PC87417) than for internal access (internal modules of the PC8741x device). If wait states are configured for the module or

X-Bus access, their duration must be added to the internal bus transaction time. When the XRDY signal is in use, its delay

must also be accounted for.

If an LPC transaction started before an ACCESS.bus transaction, the execution of the ACCESS.bus transaction through the

internal bus is withheld until the end of the LPC transaction.

Slave Address

Command

Offset Address

Data

PEC

(S.A, Write)

(XA23-XA16)

(Ext, Write, XA26-24)

= Start condition

= ACK by slave

= Stop condition

Offset Address

(XA15-XA8)

A Offset Address

(XA7-XA0)

Slave Address

Command

Offset Address

Data

PEC

(S.A, Write)

= Start condition

= Restart condition

= Stop condition

Slave Address

(S.A, Read)

= ACK by slave

A = ACK by master

= NACK by master

Offset Address A Offset Address A

(XA23-XA16)

(Ext, Read, XA26-24)

(XA15-XA8)

(XA7-XA0)

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