PC87413 datasheet(105/257 Pages) NSC

105 / 257 page

5.0 X-Bus Extension (Continued)

Revision 1.2

105

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Figure 26. Turbo Latched Address Mode - X-Bus Write Access Cycle

5.3

X-BUS PROTECTION

The PC8741x devices include a mechanism to protect the settings of the X-Bus mapping functions and the contents of the

memories mapped to it. This mechanism consists of three separate lock mechanisms, which must all be in use to obtain the

most comprehensive protection:

Lock the memory mapping by the host, using the lock bit in the X-Bus Memory Conﬁguration register and X-Bus I/O

Conﬁguration register.

Lock the bits of the X-Bus Select n Conﬁguration register and X-Bus Mode n register, using the lock bit in the respec-

tive X-Bus Mode register.

A Memory protection mechanism is available for XCS0 and XCS1. This protects the contents of up to two memory

devices (one for each chip-select) for read and/or write with a granularity of 16 blocks each. This is done using the

Host Access Protect registers 0 and 1 for XCS0 and XCS1, respectively.

Note that access protection is provided only for XCS0 and XCS1. Absolute access protection is only enabled by using all

three lock levels.

The Memory protection mechanism pertains to the X-Bus address and the chip-select (XCS0 or XCS1) involved in the trans-

action. The size of a protected block is determined by dividing the size of each BIOS Zone by 16 (see Section 3.15.12 on

page 84). Table 31 on page 106 shows the protected block size for different BIOS Zone sizes.

CLK

(Internal; for

XD7-0

XA27-0

XA11-0

XCSn

XWR_XRW

(After Latching)

[27-20]

[19-12]

XRD_XEN

XSTB2

XSTB1

XSTB0

(Availability on Device Pins

Depends on Multiplexing)

Transaction Continues as for Non-Latched, Turbo X-Bus Address Mode 0 Write

[11-4]

Starting point

[7-0]

Reference Only)

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